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參數(shù)資料
| 型號： | M5M5Y5636TG-25 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（524288 - Word的36位）網(wǎng)絡(luò)的SRAM |
| 文件頁數(shù)： | 3/27頁 |
| 文件大?。?/td> | 212K |
| 代理商： | M5M5Y5636TG-25 |
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MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
3
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5636TG REV.0.0
BLOCK DIAGRAM
Note3. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter.
Note4. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION
and timing diagrams for detailed information.
ADDRESS
REGISTER
19
WRITE ADDRESS
REGISTER1
WRITE ADDRESS
REGISTER2
A1
A0
LINEAR/
INTERLEAVED
BURST
COUNTER
D1
D0
Q1
Q0
A1'
A0'
19
17
WRITE REGISTRY
AND
DATA COHERENCY
CONTROL LOGIC
BYTE a
|
BYTE d
WRITE
DRIVERS
256Kx36
MEMORY
ARRAY
O
O
O
INPUT
REGISTER1
INPUT
REGISTER0
READ
LOGIC
19
19
36
DQa
DQPa
DQb
DQPb
DQc
DQPc
DQd
DQPd
LBO#
A0
A1
A2
~
18
CLK
E2
E3
E1#
BWa#
BWb#
BWc#
BWd#
ADV
W#
V
DD
V
DDQ
V
SS
EP2
EP3
CQ1
CQ1#
CQ2
CQ2#
E
O
CHIP ENABLE
CONTROL
LOGIC
ZQ
E
O
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