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參數(shù)資料
| 型號： | M5M5Y5636TG-25 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（524288 - Word的36位）網(wǎng)絡的SRAM |
| 文件頁數(shù)： | 19/27頁 |
| 文件大?。?/td> | 212K |
| 代理商： | M5M5Y5636TG-25 |
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MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
19
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5636TG REV.0.0
JTAG PORT OPERATION
Overview
The JTAG Port on this SRAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but dose not implement all of the function required for 1149.1 compliance. Unlike JTAG
implementations that have been common among SRAM vendors for the last several years, this implementation dose offer a form of
EXTEST, known as Clock Assisted EXTEST, reducing or eliminating the "hand coding" that has been required to overcome the test
program compiler errors caused by previous non-compliant implementation. The JTAG Port interfaces with conventional CMOS logic
level signaling.
Disabling the JTAG port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. To
assure normal operation of the SRAM with the JTAG Port unused, the TCK, TDI and TMS pins may be left floating or tied to High. The
TDO pin should be left unconnected.
JTAG Pin Description
Test Clock (TCK)
The TCK input is clock for all TAP events. All inputs are captured on the rising edge of TCK and the Test Data Out (TDO) propagates
from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP Controller state machine. An undriven TMS
input will produce the same result as a logic one input level.
Test Data In (TDI)
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between the TDI and TDO pins.
the register placed between the TDI and TDO pins is determined by the state of the TAP Controller state machine and the instruction
that is currently loaded in the TAP Instruction Resister (refer to the TAP Controller State Diagram). An undriven TDI Input will produce
the same result as a logic one input level.
Test Data Out (TDO)
The TDO output is active depending on the state of the TAP Controller state machine. Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed between the TDI and TDO pins.
Note:
This device dose not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS
is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.
JTAG Port Registers
Overview
The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequence of 1s and 0s
applied to TMS as TCK is strobed. Each of TAP Registers are serial shift registers that capture serial input data on the rising edge of
TCK and push serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP Controller when it is moved into the Run-Test/Idle, or the
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