參數(shù)資料
型號(hào)： M5M5Y5636TG-25
廠商： Mitsubishi Electric Corporation
英文描述： 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
中文描述： 18874368位（524288 - Word的36位）網(wǎng)絡(luò)的SRAM
文件頁(yè)數(shù)： 6/27頁(yè)
文件大?。?/td> 212K
代理商： M5M5Y5636TG-25
MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
6
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5636TG REV.0.0
Write Operation
Double Late Write
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3) are
active and the write enable input signal (W#) is asserted low.
Double Late Write means that Data In is required on the third rising edge of clock. It is designed to eliminate dead bus cycles when
turning the bus around between reads and writes, or writes and reads.
CLK
A
C
D
E
F
ADD
E1#
ADV
W#
BWx#
DQ
CQ
Q(A)
Q(C)
B
D(B)
D(D)
Read A
Write B
Read C
Write D
Read E
Read F
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