參數(shù)資料
型號： M7040N-100ZA1T
廠商： 意法半導(dǎo)體
英文描述： 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE
中文描述： 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎
文件頁數(shù)： 101/159頁
文件大?。?/td> 1088K
代理商： M7040N-100ZA1T
101/159
M7040N
Table 45. Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit
Table 46. Shift of SSF and SSV from SADR
288-bit Search on Tables Configured as x288 Using Up to 31 M7040N Devices
The hardware diagram of the search subsystem of
31 devices is shown in Figure 74, page 103. Each
of the four blocks in the diagram represents a
block of eight M7040N devices, except the last
which has seven devices.The diagram for a block
of eight devices is shown in Figure 75, page 104.
The following are the parameters programmed
into the 31 devices.
–
First thirty devices (devices 0
–
29):
CFG = 1010101010101010, TLSZ = 10,
HLAT = 000, LRAM = 0, and LDEV = 0.
–
Thirty-first device (device 30):
CFG = 1010101010101010, TLSZ = 10,
HLAT = 000, LRAM = 1, and LDEV = 1.
Note:
All 31 devices must be programmed with the
same value of TLSZ and HLAT. Only the last de-
vice in the table must be programmed with
LRAM = 1 and LDEV = 1 (Device 30 in this case).
All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (Devices 0 through
29 in this case).
The timing diagrams referred to in this paragraph
reference the HIT/MISS assumptions defined in
Table 47, page 103. For the purpose of illustrating
the timings, it is further assumed that there is only
one device with the matching entry in each block.
Figure 77, page 106 shows the timing diagram for
a SEARCH command in the 288-bit-configured ta-
ble consisting of 31 devices for each of the eight
devices in Block 0. Figure 78, page 107 shows the
timing diagram for a SEARCH command in the
288-bit-configured table of 31 devices for all devic-
es above the winning device in Block 1. Figure 79,
page 108 shows the timing diagram for the global-
ly winning device (the final winner within its own
and all blocks) in Block 1. Figure 80, page 109
shows the timing diagram for all the devices below
the globally winning device in Block 1. Figure 81,
page 110, Figure 82, page 111, and Figure 83,
page 112, respectively, show the timing diagrams
of the devices above the globally winning device,
the globally winning device, and the devices below
the globally winning device for Block 2. Figure 84,
page 113, Figure 85, page 114, Figure 86, page
115, and Figure 87, page 116, respectively, show
the timing diagrams of the device above the glo-
bally winning device, the globally winning device,
the devices below the globally winning device (ex-
cept Device 30), and last device (Device 30) for
Block 3.
# of devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
16K x 288-bit
4
1
–
8 (TLSZ = 01)
128K x 288-bit
5
1
–
31 (TLSZ = 10)
496K x 288-bit
6
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
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