參數(shù)資料
型號(hào)： M7040N-100ZA1T
廠(chǎng)商： 意法半導(dǎo)體
英文描述： 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE
中文描述： 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎
文件頁(yè)數(shù)： 94/159頁(yè)
文件大?。?/td> 1088K
代理商： M7040N-100ZA1T
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M7040N
94/159
288-bit SEARCH on Tables x288-configured Using Up to Eight M7040N Devices
The hardware diagram of the search subsystem of
eight devices is shown in Figure 69, page 96. The
following are the parameters programmed in the
eight devices.
–
First seven devices (devices 0
–
6):
CFG = 1010101010101010, TLSZ = 01,
HLAT = 000, LRAM = 0, and LDEV = 0.
–
Eighth device (device 7):
CFG = 1010101010101010, TLSZ = 01,
HLAT = 000, LRAM = 1, and LDEV = 1.
Note:
All eight devices must be programmed with
the same value of TLSZ and HLAT. Only the last
device in the table must be programmed with
LRAM = 1 and LDEV = 1 (Device 7 in this case).
All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (Devices 0 through
6 in this case).
Figure 71, page 98 shows the timing diagram for a
SEARCH command in the 288-bit-configured ta-
ble of eight devices for Device 0. Figure 72, page
99 shows the timing diagram for a SEARCH com-
mand in the 288-bit-configured table of eight de-
vices for Device 1. Figure 73, page 100 shows the
timing diagram for a SEARCH command in the
288-bit-configured table of eight devices for De-
vice 7 (the last device in this specific table). For
these timing diagrams three 288-bit searches are
performed sequentially. The following HIT/MISS
assumptions were made as shown in Table 44,
page 95.
The following is the sequence of operation for a
single 288-bit SEARCH command (also COM-
MAND CODES AND PARAMETERS, page 30).
–
Cycle A:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') on
CMD[1:0] signals. {CMD[10],CMD[5:3]} signals
must be driven with the index to the GMR pair
used for bits [287:144] of the data being
searched in this operation. DQ[71:0] must be
driven with the 72-bit data ([287:216]) to be
compared against all locations
“
0
”
in the four-
word, 72-bit page. The CMD[2] signal must be
driven to logic '1.'
Note:
CMD[2] = 1 signals that the search is a
288-bit search. CMD[8:3] in this cycle is ig-
nored.
–
Cycle B:
The host ASIC continues to drive the
CMDV high and applies SEARCH command
code ('10') on CMD[1:0]. The DQ[71:0] is driven
with the 72-bit data ([215:144]) to be compared
against all locations
“
1
”
in the four 72-bits-word
page.
–
Cycle C:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') on
CMD[1:0] signals. {CMD[10],CMD[5:3]} signals
must be driven with the index to the GMR pair
used for bits [143:0] of the data being searched.
CMD[8:6] signals must be driven with the bits
that will be driven on SADR[23:21] by this de-
vice if it has a hit. DQ[71:0] must be driven with
the 72-bit data ([143:72]) to be compared
against all locations
“
2
”
in the four 72-bits-word
page. The CMD[2] signal must be driven to logic
'0.'
–
Cycle D:
The host ASIC continues to drive the
CMDV high and applies SEARCH command
code ('10') on CMD[1:0]. CMD[8:6] signals must
be driven with the index of the SSR that will be
used for storing the address of the matching en-
try and the Hit Flag (see SEARCH-Successful
Registers (SSR[0:7]), page 24). The DQ[71:0] is
driven with the 72-bit data ([71:0]) to be com-
pared to all locations
“
3
”
in the four 72-bits-word
page. CMD[5:2] is ignored because the LEARN
Instruction is not supported for x288 tables.
Note:
For 288-bit searches, the host ASIC must
supply four distinct 72-bit data words on
DQ[71:0] during Cycles A, B, C, and D. The
GMR Index in Cycle A selects a pair of GMRs in
each of the eight devices that apply to DQ data
in Cycles A and B. The GMR Index in Cycle C
selects a pair of GMRs in each of the eight de-
vices that apply to DQ data in Cycles C and D.
The logical 288-bit SEARCH operation is shown in
Figure 70, page 97. The entire table of 288-bit en-
tries is compared to a 288-bit word K that is pre-
sented on the DQ Bus in Cycles A, B, C, and D of
the command using the GMR and the local mask
bits. The GMR is the 288-bit word specified by the
two pairs of GMRs selected by the GMR Indexes
in the command
’
s Cycles A and C in each of the
eight devices. The 288-bit word K that is presented
on the DQ Bus in Cycles A, B, C, and D of the com-
mand is compared to each entry in the table start-
ing at location
“
0.
”
The first matching entry
’
s
location address,
“
L,
”
is the winning address that is
driven as part of the SRAM address on the
SADR[23:0] lines (see SRAM ADDRESSING,
page 128).
Note:
The matching address is always going to be
a location
“
0
”
in a four-entry page for 288-bit
SEARCH (two LSBs of the matching index will be
'00').
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