參數(shù)資料
型號: M7040N-100ZA1T
廠商: 意法半導(dǎo)體
英文描述: 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE
中文描述: 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎
文件頁數(shù): 129/159頁
文件大小: 1088K
代理商: M7040N-100ZA1T
129/159
M7040N
Cycle 2:
The host ASIC floats DQ[71:0] to a 3-
state condition.
Cycle 3:
The host ASIC keeps DQ[71:0] in a 3-
state condition.
Cycle 4:
The selected device starts to drive
DQ[71:0] and drives ACK from High-Z to low.
Cycle 5:
The selected device drives the READ
address on SADR[23:0]; it also drives ACK high,
CE_L low, and ALE_L low.
Cycle 6:
The selected device drives CE_L high,
ALE_L high, the SADR Bus, and the DQ Bus in
a 3-state condition; it drives ACK low.
At the end of Cycle 6, the selected device floats
ACK in a 3-state condition, and a new command
can begin.
Figure 96. SRAM READ Access for One Device
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
CLK2X
CMDV
CMD[1:0]
ACK
SSV
SSF
SADR
DQ
OE_L
WE_L
CE_L
PHS_L
AI04736
READ
CMD[10:2]
A
B
Address
Address
(DQ driven by M7040)
HLAT = 000, TLSZ = 00, LRAM = 1, LDEV = 1
z
z
0
1
1
ALE_L
1
z
0
0
0
0
1
1
0
1
0
z
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