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參數資料
| 型號： | M7040N-100ZA1T |
| 廠商： | 意法半導體 |
| 英文描述： | 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| 中文描述： | 64K的× 72位的網絡數據包進入搜索引擎 |
| 文件頁數： | 90/159頁 |
| 文件大?。?/td> | 1088K |
| 代理商： | M7040N-100ZA1T |
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M7040N
90/159
Table 40. Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit
Table 41. Shift of SSF and SSV from SADR
288-bit SEARCH on Tables Configured as x288 Using a Single M7040N Device
The hardware diagram for this search subsystem
is shown in Figure 66, page 91. Figure 67, page 92
shows the timing diagram for a SEARCH com-
mand in the 288-bit-configured table (CFG =
1010101010101010) consisting of a single device
for one set of parameters: TLSZ = '00,' HLAT =
'001,' LRAM = '1,' and LDEV = '1.'
The following is the sequence of operation for a
single 144-bit SEARCH command (also refer to
COMMAND CODES AND PARAMETERS, page
30).
–
Cycle A:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') on
CMD[1:0] signals. {CMD[10],CMD[5:3]} signals
must be driven with the index to the GMR pair
used for bits [287:144] of the data being
searched. DQ[71:0] must be driven with the 72-
bit data ([287:216]) to be compared to all loca-
tions
“
0
”
in the four 72-bits-word page. The
CMD[2] signal must be driven to logic
“
1.
”
Note:
CMD[2] = 1 signals that the search is a
x288-bit search. CMD[8:3] in this cycle is ig-
nored.
–
Cycle B:
The host ASIC continues to drive the
CMDV high and continues to apply the com-
mand code of SEARCH command ('10') on
CMD[1:0]. The DQ[71:0] is driven with the 72-bit
data ([215:144]) to be compared to all locations
“
1
”
in the four 72-bits-word page.
–
Cycle C:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') on
CMD[1:0] signals. {CMD[10],CMD[5:3]} signals
must be driven with the index to the GMR pair
used for bits [143:0] of the data being searched.
CMD[8:6] signals must be driven with the bits
that will be driven on SADR[23:21] by this de-
vice if it has a hit. DQ[71:0] must be driven with
the 72-bit data ([143:72]) to be compared to all
locations
“
2
”
in the four 72-bits-word page. The
CMD[2] signal must be driven to logic '0.'
–
Cycle D:
The host ASIC continues to drive the
CMDV high and applies SEARCH command
code ('10') on CMD[1:0]. CMD[8:6] signals must
be driven with the index of the SSR that will be
used for storing the address of the matching en-
try and the Hit Flag (see SEARCH-Successful
Registers (SSR[0:7]), page 24). The DQ[71:0] is
driven with the 72-bit data ([71:0]) to be com-
pared to all locations
“
3
”
in the four 72-bits-word
page. CMD[5:2] is ignored because the LEARN
Instruction is not supported for x288 tables.
Note:
For 288-bit searches, the host ASIC must
supply four distinct 72-bit data words on
DQ[71:0] during Cycles A, B, C, and D. The
GMR Index in Cycle A selects a pair of GMRs
that apply to DQ data in Cycles A and B. The
GMR Index in Cycle C selects a pair of GMRs
that apply to DQ data in Cycles C and D.
# of devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
32K x 144-bit
4
1
–
8 (TLSZ = 01)
256K x 144-bit
5
1
–
31 (TLSZ = 10)
992K x 144-bit
6
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
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