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參數(shù)資料
| 型號(hào)： | M7040N-100ZA1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| 中文描述： | 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎 |
| 文件頁(yè)數(shù)： | 117/159頁(yè) |
| 文件大?。?/td> | 1088K |
| 代理商： | M7040N-100ZA1T |
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M7040N
Table 48. Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit
Table 49. Shift of SSF and SSV from SADR
MIXED SEARCHES
Tables Configured with Different Widths Using
an M7040N with CFG_L LOW
The sample operation shown is for a single device
with CFG = 1010010100000000. It contains three
tables of x72, x144, and x288 widths. The opera-
tion may be generalized to a block of 8
–
31 devices
using four blocks; the timing and the pipeline oper-
ation is the same as described previously for fixed
searches on a table of one-width-size.
Figure 88, page 118 shows three sequential
searches:
–
a 72-bit search on the table configured as x72;
–
a 144-bit search on a table configured as x144;
and
–
a 288-bit search on the table configured as x288
bits that each results in a hit.
Note:
The DQ[71:70] will be '00' in both of the Cy-
cles A and B of the x72-bit search (Search1).
DQ[71:70] is '01' in both of the Cycles A and B of
the x144-bit search (Search2). DQ[71:70] is '10' in
all of the Cycles A, B, C, and D of the x288-bit
search (Search 3). By having table designation
bits, the M7040N enables the creation of many ta-
bles in a bank of search engines of different
widths.
Figure 89, page 119 shows the sample table. Two
bits in each 72-bit entry will need to designated as
the Table Number Bits. One example choice can
be the '00' values for the table configured as x72,
'01' values for tables configured as x144, and '10'
values for tables configured as x288. For the
above explanation, it is further assumed that bits
[71:70] for each entry will be designed as these
Table Designation Bits.
Tables ConfiguredtoDifferentWidthsusingan
M7040N with CFG_L HIGH
Searches on tables of different widths using Table
Designation Bits in the data array can be wasteful
of these bits. In order to avoid wasting these bits
and still support up to three tables of x72, x144,
and x288, the CMD[2] and CMD[9] (in CFG_L high
mode) in Cycle A of the command can be used as
shown in Table 50, page 119.
# of devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
16K x 288-bit
4
2
–
8 (TLSZ = 01)
128K x 288-bit
5
2
–
31 (TLSZ = 10)
496K x 288-bit
6
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
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