- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377835 > M7040N-100ZA1T (意法半導(dǎo)體) 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE PDF資料下載
參數(shù)資料
| 型號(hào)： | M7040N-100ZA1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| 中文描述： | 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎 |
| 文件頁(yè)數(shù)： | 74/159頁(yè) |
| 文件大小： | 1088K |
| 代理商： | M7040N-100ZA1T |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)當(dāng)前第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)
M7040N
74/159
Table 37. Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit
Table 38. Shift of SSF and SSV from SADR
144-bit Search on Tables Configured as x144 Using Up to 31 M7040N Devices
The hardware diagram of the search subsystem of
31 devices is shown in Figure 52, page 76. Each
of the four blocks in the diagram represents a
block of eight M7040N devices (except the last,
which has seven devices).The diagram for a block
of eight devices is shown in Figure 53, page 77.
Following are the parameters programmed into
the 31 devices.
First thirty devices (devices 0
–
29):
CFG = 0101010101010101, TLSZ = 10,
HLAT = 001, LRAM = 0, and LDEV = 0.
Thirty-first device (device 30):
CFG = 0101010101010101, TLSZ = 10,
HLAT = 001, LRAM = 1, and LDEV = 1.
Note:
All 31 devices must be programmed with the
same value of TLSZ and HLAT. Only the last de-
vice in the table must be programmed with
LRAM = 1 and LDEV = 1 (Device 30 in this case).
All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (Devices 0 through
29 in this case).
The timing diagrams referred to in this paragraph
reference the HIT/MISS assumptions defined in
Table 39, page 75. For the purpose of illustrating
timings, it is further assumed that the there is only
one device with a matching entry in each of the
blocks. Figure 55, page 79 shows the timing dia-
gram for a SEARCH command in the 144-bit-con-
figured table (31 devices) for each of the eight
devices in Block 0. Figure 56, page 80 shows the
timing diagram for SEARCH command in the
72-bit-configured table (31 devices) for all the de-
vices in Block 1 above the winning device in that
block. Figure 57, page 81 shows the timing dia-
gram for the globally winning device (the final win-
ner within its own block and all blocks) in Block 1.
Figure 58, page 82 shows the timing diagram for
all the devices below the globally winning device in
Block 1. Figure 59, page 83, Figure 60, page 84,
and Figure 61, page 85 respectively show the tim-
ing diagrams of the devices above globally win-
ning device, the globally winning device and
devices below the globally winning device for
Block 2. Figure 62, page 86, Figure 63, page 87,
Figure 64, page 88, and Figure 65, page 89 re-
spectively show the timing diagrams of the devices
above the globally winning device, the globally
winning device, and devices below the globally
winning device except the last device (Device 30),
and the last device (Device 30) for Block 3.
# of devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
32K x 144-bit
4
1
–
8 (TLSZ = 01)
256K x 144-bit
5
1
–
31 (TLSZ = 10)
992K x 144-bit
6
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M708 | PCM REMOTE CONTROL TRANSMITTER |
| M708A | PCM REMOTE CONTROL TRANSMITTER |
| M708B1 | PCM REMOTE CONTROL TRANSMITTER |
| M708AB1 | PCM REMOTE CONTROL TRANSMITTER |
| M709 | PCM REMOTE CONTROLL TRANSMITTERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7041 | 制造商:Tamura Corporation of America 功能描述: |
| M7045 | 制造商:Tamura Corporation of America 功能描述: |
| M705-5090142 | 功能描述:直流電源連接器 FEMALE STEREO JACK RoHS:否 制造商:Kycon 產(chǎn)品:Receptacles 觸點(diǎn)內(nèi)徑: 觸點(diǎn)外徑: 中心腳長(zhǎng)度: 電流額定值:7.5 A 電壓額定值:20 V 安裝角:Right 安裝風(fēng)格:Cable |
| M705-5090242 | 功能描述:RCA Phono連接器 FEMALE STEREO JACK RoHS:否 制造商:Neutrik 型式:Male 端接類型:Solder 安裝風(fēng)格:Cable 方向:Horizontal |
| M705-510046 | 功能描述:RCA Phono連接器 DC JACKS RoHS:否 制造商:Neutrik 型式:Male 端接類型:Solder 安裝風(fēng)格:Cable 方向:Horizontal |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。