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參數(shù)資料
| 型號： | M7040N-100ZA1T |
| 廠商： | 意法半導體 |
| 英文描述： | 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| 中文描述： | 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進入搜索引擎 |
| 文件頁數(shù)： | 35/159頁 |
| 文件大?。?/td> | 1088K |
| 代理商： | M7040N-100ZA1T |
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M7040N
Table 21. READ Address Format for Internal Registers
Table 22. READ Address Format for Data and Mask Arrays
WRITE COMMAND
The WRITE can be a single write of a data array,
mask array, register, or external SRAM location
(CMD[2]
=
0).
It
can
(CMD[2] = 1) using an internal auto-incrementing
address register (WBURADR) of the data array or
mask array locations. A single-location WRITE is a
three-cycle operation, shown in Figure 20, page
36. The burst WRITE adds one extra cycle for
each successive WRITE.
The WRITE operation sequence is as follows:
–
Cycle 1A:
The host ASIC applies the WRITE In-
struction on the CMD[1:0] (CMD[2] = 0), using
CMDV=1 and the address supplied on the DQ
Bus, as shown in Table 23, page 37. The host
ASIC also supplies the index to the global mask
register to mask the write to the data array or
mask array location in {CMD[10], CMD[5:3]}.
For SRAM WRITEs, the host ASIC must supply
the SADR[23:21] on CMD[8:6]. The host ASIC
sets CMD[9] to '0' for the normal WRITE.
–
Cycle 1B:
The host ASIC continues to apply the
WRITE
Instruction
(CMD[2] = 0), using CMDV = 1 and the address
supplied on the DQ Bus. The host ASIC contin-
ues to supply the global mask register index to
mask the WRITE to the data or mask array loca-
tions in {CMD[10], CMD[5:3]}. The host ASIC
selects the device where ID[4:0] matches the
DQ[25:21] lines, or it selects all the devices
when DQ[25:21] = 11111.
–
Cycle 2:
The host ASIC drives the DQ[71:0]
with the data to be written to the data array,
mask array, external SRAM, or register location
of the selected device.
be
a
burst
WRITE
to
the
CMD[1:0]
–
Cycle 3:
Idle cycle. At the termination of this cy-
cle, another operation can begin.
Note:
The latency of the SRAM WRITE will be
different than the one described above (see
SRAM PIO Access, page 128).
The burst WRITE operation lasts for n + 2 CLK cy-
cles (where n signifies the number of accesses in
the burst as specified in the BLEN field of the
WBURREG register, please see Figure 21, page
37).
This operation assumes that the host ASIC has
programmed the WBURREG with the starting ad-
dress (ADR) and the length of transfer (BLEN) be-
fore initiating the burst write command (see Table
25, page 38 for format). The sequence is as fol-
lows:
–
Cycle 1A:
The host ASIC applies the WRITE In-
struction on the CMD[1:0] (CMD[2] = 1), using
CMDV = 1 and the address supplied on the DQ
Bus, as shown in Table 25, page 38. The host
ASIC also supplies the index to the global mask
register to mask the write to the data or mask ar-
ray locations in {CMD[10], CMD[5:3]}. The host
ASIC sets ASIC sets CMD[9] to '0' for the nor-
mal WRITE.
–
Cycle 1B:
The host ASIC continues to apply the
WRITE
Instruction
(CMD[2] = 0), using CMDV = 1 and the address
supplied on the DQ Bus. The host ASIC contin-
ues to supply the global mask register index to
mask the WRITE to the data or mask array loca-
tions in {CMD[10], CMD[5:3]}. The host ASIC
selects the device where ID[4:0] matches the
DQ[25:21] lines, or it selects all the devices
when DQ[25:21] = 11111.
on
the
CMD[1:0]
DQ[71:26]
DQ[25:21]
DQ[20:19]
DQ[18:7]
DQ[6:0]
Reserved
ID
11: Register
Reserved
Register Address
DQ[71:26]
DQ[25:21]
DQ[20:19]
DQ[18:16]
DQ[15:0]
Reserved
ID
00: Data Array
Reserved
Do not care. These 16 bits come from the internal
register (RBURADR) which increments for each
access.
Reserved
ID
01: Mask
Array
Reserved
Do not care. These 16 bits come from the internal
register (RBURADR) which increments for each
access.
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