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MB90560 series
CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT
;-------Vector setting-----------------------------------------------------------------------------------------------------
VECT
CSEG
ABS=0FFH
ORG
0FF98H
; Sets vector for interrupt #25 (19H).
DSL
WARI
ORG
0FFDCH
; Sets reset vector.
DSL
START
DB
00H
; Sets single-chip mode.
VECT
ENDS
END
START
I
Sample program for the DTP function
G
Processing
The H level of the signal input to the INT0 pin is detected, and channel 0 of the extended
intelligent I/O service (EI
2
OS) is activated.
Data is output from RAM to port 0 by DTP processing (EI
2
OS).
G
Coding example
ICR07
EQU
0000B6H
; Interrupt control register for the DTP/external
; interrupt circuit
; Port 0 direction register
; Port 1 direction register
; DTP/interrupt enable register
; DTP/interrupt cause register
; Request level setting register
; Request level setting register
; INT0 interrupt flag bit
; INT0 interrupt enable bit
; Buffer address pointer, lower
; Buffer address pointer, middle
; Buffer address pointer, upper
; EI
2
OS status register
; I/O address register, lower
; I/O address register, upper
; Data counter, lower
; Data counter, upper
DDR0
DDR1
ENIR
EIRR
ELVRL
ELVRH
ER0
EN0
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
;-------Main program------------------------------------------------------------------------------------------------------
----------
CODE
CSEG
START:
;
:
; Assumes that stack pointer (SP) has already been
initialized.
MOV
I:DDR0,#11111111B ; Sets DDR0 as an output port.
MOV
I:DDR1,#00000000B ; Sets DDR1 as an input port.
AND
CCR,#0BFH
; Disables interrupts.
MOV
I:ICR07,#08H
; Interrupt level: 0 (highest)
; Enables EI
2
OS. Channel 0
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000010H
000011H
000030H
000031H
000032H
000033H
EIRR:0
ENIR:0
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H