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2.7
2.7.6 Interrupt level mask register (PS: ILM)
Dedicated Registers
MB90560 series
CHAPTER 2 CPU
51
The interrupt level mask register (ILM) is a 3-bit register that indicates the level of the
interrupt currently accepted by the CPU.
I
Interrupt level mask register (ILM)
Figure 2.7-12 shows the configuration of the interrupt level mask register (ILM). See Chapter 6,
"Interrupts," for details about interrupts.
Figure 2.7-12 Configuration of the interrupt level mask register (ILM)
The interrupt level mask register (ILM) indicates the level of the interrupt currently accepted by
the CPU. The level is compared with the value of the IL0 to IL2 bits of the interrupt control
register (ICR00 to ICR15) set according to the interrupt request from the peripheral function. If
the interrupt enable flag has been set to enable (CCR: I = 1), the CPU processes the instruction
only when the value (interrupt level) of the interrupt request is smaller than the value indicated by
these bits.
When an interrupt is accepted, the interrupt level value is set in the interrupt level mask
register (ILM). Thereafter, interrupts with the same or lower level are not accepted.
The interrupt level is set to the highest level, which is the interrupts disabled status, because
the interrupt level mask register (ILM) is initialized to all 0s by a reset.
Although an assembler instruction can use an 8-bit immediate value transfer instruction for
transfer to the interrupt level mask register (ILM), only the lower 3 bits of the data are used.
Table 2.7-3 Interrupt level mask register (ILM) and interrupt level priority
ILM2
ILM1
ILM0
Interrupt level
Interrupt level priority
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
Highest (interrupts disabled)
Lowest
ILM initial value