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CHAPTER 3 RESETS
MB90560 series
3.1
Resets
If a reset cause is generated, the CPU immediately stops the current execution process
and waits for the release of the reset. When the reset is released, the CPU begins
processing at the address indicated by the reset vector.
There are four causes of a reset:
Power-on reset
Watchdog timer overflow
External reset request via the RSTX pin
Software reset request
I
Reset causes
Table 3.1-1 lists the reset causes.
Table 3.1-1 Reset causes
MCLK: Main clock (oscillation clock divided by 2)
G
External reset
An external reset is generated by the “L” level input to an external reset pin (RSTX pin). The
minimum required period of the “L” level input to the RSTX pin is 16 machine cycles (16/
φ
). The
oscillation stabilization wait interval is not required for external resets.
<Reference>
For external reset requests via the RSTX pin, if the reset cause is generated during a write
operation (during the execution of a transfer instruction such as MOV), the CPU waits for the
reset to be released after the instruction is completed. The normal write operation is therefore
completed even though a reset is input concurrently.
Note, however, that waiting for the reset to be released may not start before the transfer of
the contents of a counter specified by a string-processing instruction (such as MOVS) is
completed.
Type of reset
Cause
Machine clock
Watchdog timer
Oscillation
stabilization
wait
External pin
“L” level input to RST pin
Previous state
retained
Previous state
retained
No
Software
A “0” is written to the RST bit of
the low power consumption
mode control register (LPMCR).
Watchdog timer overflow
When the power is turned on
Previous state
retained
Previous state
retained
No
Watchdog timer
Power-on
MCLK
MCLK
Stop
Stop
Yes
Yes