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參數(shù)資料
| 型號： | MBM29F040A-90 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4M (512K ×8) BIT Flash Memoery(512K ×8位 5V 電源電壓閃速存儲器) |
| 中文描述： | 4分（為512k × 8）位閃存Memoery（為512k × 8位5V的電源電壓閃速存儲器） |
| 文件頁數(shù)： | 12/42頁 |
| 文件大?。?/td> | 492K |
| 代理商： | MBM29F040A-90 |
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12
MBM29F040A
-70/-90/-12
Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until
the command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A
9
to a high voltage (V
ID
= 11.5 V to 12.5). However,
multiplexing high voltage onto the address lines is not generally desired system design practice.
The device contains an autoselect command operation to supplement traditional PROM programming method-
ology. The operation is initiated by writing the autoselect command sequence into the command register. Fol-
lowing the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address XX01H returns the device code A4H. (see Table 3.) All manufacturer and device codes will
exhibit odd parity with the MSB (DQ
7
) defined as the parity bit.
Sector state (protection or unprotection) will be informed address XX02H.
Scanning the sector addresses (A
16
, A
17
, A
18
) while (A
6
, A
1
, A
0
) = (0, 1, 0) will produce a logical “1” at device
output DQ
0
for a protected sector.
To terminate the operation, it is necessary to write the read/reset command sequence into the register.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses
are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge
of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins program-
ming. Upon executing the Embedded Program Algorithm command sequence the system is not required to
provide further controls or timings. The device will automatically provide adequate internally generated program
pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit (see Write Operation Status section.) at which time the device returns to the read mode and addresses are
no longer latched. Therefore, the device requires that a valid address to the device be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so will probably hang up the device (exceed timing limits.), or
perhaps result in an apparent success according to the data polling algorithm but a read from reset/read mode
will show that the data is still “0”. Only erase operations can convert “0”s to “1”s.
Figure 11 illustrates the Embedded Programming Algorithm using typical command strings and bus operations.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29F040A | 4M (512K ×8) Bit Flash Memory( 單5V 電源電壓512K ×8位閃速存儲器) |
| MBM29F040C | 4M (512K X 8) BIT |
| MBM29F040C-55 | Replaced by TPS2041B : 0.7A, 2.7-5.5V Single Hi-Side MOSFET, Fault Report, Act-Low Enable 8-PDIP -40 to 85 |
| MBM29F040C-55PD | 4M (512K X 8) BIT |
| MBM29F040C-55PFTN | Replaced by TPS2041B : 0.7A, 2.7-5.5V Single Hi-Side MOSFET, Fault Report, Act-Low Enable 8-SOIC 0 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F040A-90-X | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:FLASH MEMORY CMOS 4M 512K X 8 BIT |
| MBM29F040C | 制造商:FUJRTSU 功能描述: |
| MBM29F040C-55 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29F040C-55PD | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29F040C-55PFTN | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY 4M (512K x 8) BIT |
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