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參數(shù)資料
| 型號： | MBM29F040A-90 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4M (512K ×8) BIT Flash Memoery(512K ×8位 5V 電源電壓閃速存儲器) |
| 中文描述： | 4分（為512k × 8）位閃存Memoery（為512k × 8位5V的電源電壓閃速存儲器） |
| 文件頁數(shù)： | 15/42頁 |
| 文件大?。?/td> | 492K |
| 代理商： | MBM29F040A-90 |
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MBM29F040A
-70/-90/-12
an attempt to read the device will produce the true data last written to DQ
7
. During the Embedded Erase
Algorithm, an attempt to read the device will produce a “0” at the DQ
7
output. Upon completion of the Embedded
Erase Algorithm an attempt to read the device will produce a “1” at the DQ
7
output. The flowchart for Data Polling
(DQ
7
) is shown in Figure 13.
For chip erase, and sector erase the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase
WE pulse. Data Polling must be performed at sector address within any of the sectors being erased and not a
protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to
being completed, the MBM29F040A data pins (DQ
7
) may change asynchronously while the output enable (OE)
is asserted low. This means that the device is driving status information on DQ
7
at one instant of time and then
that byte's valid data at the next instant of time. Depending on when the system samples the DQ
7
output, it may
read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ
7
has a valid data, the data outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will be read
on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algo-
rithm, or sector erase time-out (see Table 6).
See Figure 8 for the Data Polling timing specifications and diagrams.
DQ
6
Toggle Bit
The MBM29F040A also features the “Toggle Bit” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ
6
will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write
pulse sequence. For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse.
The Toggle Bit is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2
μ
s and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100
μ
s
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
cause DQ6 to toggle. (See Figure 9 for the Toggle Bit timing specifications and diagrams.)
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
5
will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the device under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Table 2.
If this failure condition occurs during sector erase operation, it specifies that a particular sector is bad and it may
not be reused, however, other sectors are still functional and may be used for the program or erase operation.
The device must be reset to use other sectors. Write the Reset command sequence to the device, and then
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29F040A | 4M (512K ×8) Bit Flash Memory( 單5V 電源電壓512K ×8位閃速存儲器) |
| MBM29F040C | 4M (512K X 8) BIT |
| MBM29F040C-55 | Replaced by TPS2041B : 0.7A, 2.7-5.5V Single Hi-Side MOSFET, Fault Report, Act-Low Enable 8-PDIP -40 to 85 |
| MBM29F040C-55PD | 4M (512K X 8) BIT |
| MBM29F040C-55PFTN | Replaced by TPS2041B : 0.7A, 2.7-5.5V Single Hi-Side MOSFET, Fault Report, Act-Low Enable 8-SOIC 0 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F040A-90-X | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:FLASH MEMORY CMOS 4M 512K X 8 BIT |
| MBM29F040C | 制造商:FUJRTSU 功能描述: |
| MBM29F040C-55 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29F040C-55PD | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT |
| MBM29F040C-55PFTN | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY 4M (512K x 8) BIT |
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