參數(shù)資料
型號(hào)： MBM29F040A-90
廠(chǎng)商： Fujitsu Limited
英文描述： 4M (512K ×8) BIT Flash Memoery(512K ×8位 5V 電源電壓閃速存儲(chǔ)器)
中文描述： 4分（為512k × 8）位閃存Memoery（為512k × 8位5V的電源電壓閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 13/42頁(yè)
文件大小： 492K
代理商： MBM29F040A-90
13
MBM29F040A
-70/-90/-12
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device automatically will program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ
7
is “1” (see Write Operation Status section.) at which time the device returns to read the
mode.
Figure 12 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing
the “set-up” command. Two more “unlock” write cycles are then followed by the sector erase command. The
sector address (Any address location within the desired sector.) is latched on the falling edge of WE, while the
μ
s from the rising edge of the last
sector erase command will initiate the sector erase command(s).
Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be
concurrently erased. The time between writes must be less than 50
μ
s, otherwise that command will not be
accepted. It is recommended that processor interrupts be disabled during this time to guarantee this condition.
The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50
μ
s from the
rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of
the WE occurs within the 50
μ
s time-out window the timer is reset. (Monitor DQ
3
to determine if the sector erase
timer window is still open, see section DQ
3
, Sector Erase Timer.) Any command other than Sector Erase or
Erase Suspend during this time-out period will reset the device to read mode, ignoring the previous command
string. Resetting the device after it has begun execution will result in the data of the operated sectors being
undefined (messed up). In that case, restart the erase on those sectors and allow them to complete. (Refer to
the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be
done in any sequence and with any number of sectors (1 to 7).
Sector erase does not require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors
the remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50
μ
s time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ
7
is “1” (See Write Operation Status section.)
at which time the device returns to read mode. During the execution of the Sector Erase command, only the
Erase Suspend and Erase Resume commands are allowed. All other commands will reset the device to read
mode. Data polling must be performed at an address within any of the sectors being erased.
Figure 12 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to interrupt the chip and then do data reads (not program) from
a non-busy sector while it is in the middle of a Sector Erase operation (which may take up to several seconds).
This command is applicable ONLY during the Sector Erase operation and will be ignored if written during the
相關(guān)PDF資料
PDF描述
MBM29F040A 4M (512K ×8) Bit Flash Memory( 單5V 電源電壓512K ×8位閃速存儲(chǔ)器)
MBM29F040C 4M (512K X 8) BIT
MBM29F040C-55 Replaced by TPS2041B : 0.7A, 2.7-5.5V Single Hi-Side MOSFET, Fault Report, Act-Low Enable 8-PDIP -40 to 85
MBM29F040C-55PD 4M (512K X 8) BIT
MBM29F040C-55PFTN Replaced by TPS2041B : 0.7A, 2.7-5.5V Single Hi-Side MOSFET, Fault Report, Act-Low Enable 8-SOIC 0 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MBM29F040A-90-X 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:FLASH MEMORY CMOS 4M 512K X 8 BIT
MBM29F040C 制造商:FUJRTSU 功能描述:
MBM29F040C-55 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT
MBM29F040C-55PD 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:4M (512K X 8) BIT
MBM29F040C-55PFTN 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:FLASH MEMORY 4M (512K x 8) BIT
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