參數資料
型號： MBM29LV400B-10
廠商： Fujitsu Limited
英文描述： CMOS 4M (512K ×8/256K×16) Falsh Memory(512K ×8/256K×16位 單5V 電源電壓閃速存儲器)
中文描述： 的CMOS 4分（為512k × 8/256K × 16）Falsh存儲器（為512k × 8/256K × 16位單5V的電源電壓閃速存儲器）
文件頁數： 23/51頁
文件大?。?/td> 498K
代理商： MBM29LV400B-10
23
MBM29LV400T
-10/-12
/MBM29LV400B
-10/-12
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV400T/400B devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
0
to DQ
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
15
/A
-1
pin
becomes the lowest address bit and DQ
8
to DQ
14
bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ
0
to DQ
7
and the DQ
8
to DQ
15
bits are ignored. Refer
to Figures 13 and 14 for the timing diagram.
Data Protection
The MBM29LV400T/400B are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 2.3 V (typically 2.4 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the devices will reset to the read mode. Subsequent writes will be ignored
until the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when V
CC
is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Handling of SON Package
The metal portion of marking side is connected with internal chip electrically. Please pay attention not to occur
electrical connection during operation. In worst case, it may be caused permanent damage to device or system
by excessive current.
相關PDF資料
PDF描述
MBM29LV400B CMOS 4M (512K ×8/256K×16) Falsh Memory(512K ×8/256K×16位 單5V 電源電壓閃速存儲器)
MBM29LV400T CMOS 4M (512K ×8/256K×16) Falsh Memory(512K ×8/256K×16位 單5V 電源電壓閃速存儲器)
MBM29LV400TC-90 4M (512K X 8/256K X 16) BIT
MBM29LV400TC-90PBT 4M (512K X 8/256K X 16) BIT
MBM29LV400TC-90PF 4M (512K X 8/256K X 16) BIT
相關代理商/技術參數
參數描述
MBM29LV400BC 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT
MBM29LV400BC-12 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT
MBM29LV400BC-12PBT 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT
MBM29LV400BC-12PCV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT
MBM29LV400BC-12PF 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT
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