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參數(shù)資料
| 型號： | MC33989 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip with High Speed CAN Transceiver(帶高速CAN收發(fā)器的系統(tǒng)基片) |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的高速CAN收發(fā)器（帶高速的CAN收發(fā)器的系統(tǒng)基片） |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 676K |
| 代理商： | MC33989 |
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MC33989
15
MC33989
note1: Wdogb stays low until the Watchdog register is properly addressed through SPI.
Figure 6. Reset and Wdogb functions diagram in mode 1 and 2
4.9
Wake Up capabilities
Several wake-up capabilities are available for the device when it is in sleep or stop mode. When a wake up has occurred, the
wake up event is stored into the WUR or CAN registers. The MCU can then access to the wake up source. The wake up options
are selectable trough SPI while the device is in normal or standby mode and prior to go to enter low power mode (sleep or stop
mode). When a wake up occurs from sleep mode the device activates Vdd1. It generates an interrupt if wake up occurs from stop
mode.
4.9.1
Wake up from wake up inputs (L0, L1, L2, L3) without cyclic sense
The wake up lines are dedicated to sense external switches state and if changes occur to wake up the MCU (In sleep or stop
modes). The wake up pins are able to handle 40V DC. The internal threshold is 3V typical and these inputs can be used as input
port expander. The wake up inputs state can be read through SPI (register WUR).
In order to select and activate direct wake up from the Lx inputs the WUR register must be configured with the appropriate
level sensitivity, and the LPC register must be configured with 0xx0 data (bit LX2HS1 set at 0 and bit HS1AUTO set at 0).
Level sensitivity is selected by WUR register. Level sensitivity are configured by pair of Lx inputs: L0 and L1 level sensitvity are
configured toghether, L2 and L3 are configured toghether.
4.9.2
Cyclic sense wake up (Cyclic sense timer and wake up inputs L0, L1, L2, L3)
The SBC can wake up upon state change of one of the four wake up input lines (L0, L1, L2 and L3) while the external pull up
or pull down resistor of the switches associated to the wake up input lines are biased with HS1 Vsup switch. The HS1 switch is
activated in sleep or stop mode from an internal timer. Cyclic sense and Forced wake up are exclusive. If Cyclic Sense is enabled
the forced up can not be enabled.
In order to select and activate the cyclic sense wake up from the Lx inputs the WUR register must be configured with the
appropriate level sensitivity, and the LPC register must be configured with 1xx1 data (bit LX2HS1 set at 1 and bit HS1AUTO set at
1). The wake up mode selection (direct or cyclic sense) is valid for all 4 wake up inputs.
4.9.3
Forced wake up
SBC can wake up automatically after a pre determined time spent in sleep or stop mode. Cyclic sense and Forced wake up
are exclusive. If Forced wake up is enabled (FWU bit set to 1 in LPC register) the Cyclic Sense can not be enabled.
4.9.4
CAN interface wake up
The device incorporates a high speed 1MBaud CAN physical interface. Its electrical parameters for the CANL, CANH, Rx
For More Information On This Product,
Go to: www.freescale.com
Vdd1 < Rst-th
1
high
low
Watchdog time out reached
1
low (note1)
low
- Vdd1 normal
- Watchdog properly triggered
2 (safe mode)
high
high
Vdd1 < Rst-th
2 (safe mode)
high
low
Watchdog time out reached
2 (safe mode)
low (note1)
high
Events
Mode
WDOGB
output
Reset
output
Reset
WDOGB
Vdd1
SPI
SPI CSB
Watchdog time out
Watchdog
register
addressed
Watchdog
period
W/D clear
MODE 1
Reset
MODE 2
WDOGB
F
Freescale Semiconductor, Inc.
n
.
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| MC33990D | 功能描述:IC TRANSCEIVER J-1850 BUS 8-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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