參數(shù)資料
型號: MC33989
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip with High Speed CAN Transceiver(帶高速CAN收發(fā)器的系統(tǒng)基片)
中文描述: 系統(tǒng)基礎(chǔ)芯片的高速CAN收發(fā)器(帶高速的CAN收發(fā)器的系統(tǒng)基片)
文件頁數(shù): 4/32頁
文件大?。?/td> 676K
代理商: MC33989
MC33989
4
MC33989
Dropout Voltage
Vdd1drop
0.2
0.5
V
Idd1 = 200mA
Dropout Voltage, limited output current
Vdd1dp2
0.1
0.25
V
Idd1 = 50mA
4.5V< Vsup
Idd1 output current
Idd1
200
285
350
mA
Internally limited
Thermal Shutdown (junction)
Tsd
160
200
°C
Normal or standby mode
Over temperature pre warning (junction)
Tpw
125
160
°C
VDDTEMP bit set
Temperature Threshold difference
Tsd-Tpw
20
40
°C
Reset threshold 1
Rst-th1
4.5
4.6
4.7
V
Selectable by SPI. Default
value after reset.
Reset threshold 2
Rst-th2
4.1
4.2
4.3
V
Selectable by SPI
Vdd1 range for Reset Active
Vdd
r
1
V
Reset Delay Time
t
d
4
30
us
Measured at 50% of reset
signal
Line Regulation
(C at Vdd1= 47uF tantal)
LR1
5
25
mV
9V<V
sup
<18, I
dd
=10mA
5.5V<V
sup
<27V, I
dd
=10mA
1mA<I
Idd
<200mA
Vsup=13.5V, I=100mA
not tested, guaranted by
charaterization and design
Line Regulation
(C at Vdd1= 47uF tantal)
LR2
10
25
mV
Load Regulation
(C at Vdd1= 47uF tantal)
LD
25
75
mV
Thermal stability
ThermS
30
50
mV
Vdd1 in Stop mode
Vdd1 Output Voltage
Vddstop
4.75
5,00
5.25
V
Idd1<=2mA
Vdd1 Output Voltage
Vddstop2
4.75
5,00
5.25
V
Idd1<=10mA
Idd1 stop output current to wake up SBC
Idd1s-wu
10
17
25
mA
Idd1 over current wake up deglitcher time
Idd1 - dglt
40
55
75
us
guaranted by design
Reset threshold
Rst-stop1
4.5
4.6
4.7
V
Reset threshold
Rst-stop2
4.1
4.2
4.3
V
Line regulation
(C at Vdd1= 47uF tantal)
LR-s
5
25
mV
5.5V<V
sup
<27V, I
dd
=2mA
1mA<I
Idd
<10mA
Load regulation
(C at Vdd1= 47uF tantal)
LD-s
15
75
mV
V2 tracking voltage regulator
note 3: V2 specification with external capacitor
- Stability requirement: C>42uF and ESR<1.3 ohm (tantalum capacitor), external resistor between base and emitter required.
- Measurement conditions: Ballast transistor MJD32C, C=10uF tantalum, 2.2k resistor between base and emitter of ballast transistor.
V2 Output Voltage
(C at V2 = 10uF tantal)
V2
0.99
1
1.01
Vdd1
I2 from 2 to 200mA
5.5V< Vsup <27V
I2 output current (for information only)
I2
200
mA
Depending upon external
ballast transistor
V2 ctrl drive current capability
I2ctrl
0
10
mA
Worst case at Tj=125°C
V2LOW Flag Threshold
V2Lth
3.75
4
4.25
V
Logic output pins (MISO) Push pull structure with tri state condition (CSB high).
Low Level Output Voltage
Vol
0
1.0
V
I out = 1.5mA
High Level Output Voltage
Voh
Vdd1-0.9
Vdd1
V
I out = -250uA
Tristated MISO Leakage Current
-2
+2
uA
0V<V
miso
<Vdd
Logic input pins (MOSI, SCLK, CSB)
High Level Input Voltage
Vih
0.7Vdd1
Vdd1+0.3
Low Level Input Voltage
Vil
-0.3
0.3Vdd1
V
High Level Input Current on CSB
Iih
-100
-20
uA
V
i
=4V
V
i
=1V
0<V
IN
<Vdd
Low Level Input Current CSB
Iil
-100
-20
uA
MOSI, SCK Input Current
Iin
-10
10
uA
(V
sup
From 5.5V to 18V and Tamb -40°C to 125°C)
For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section
Description
Symbol
Characteristics
Unit
Conditions
Min
Typ
Max
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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