參數(shù)資料
型號: MC33989
廠商: 飛思卡爾半導體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip with High Speed CAN Transceiver(帶高速CAN收發(fā)器的系統(tǒng)基片)
中文描述: 系統(tǒng)基礎(chǔ)芯片的高速CAN收發(fā)器(帶高速的CAN收發(fā)器的系統(tǒng)基片)
文件頁數(shù): 25/32頁
文件大?。?/td> 676K
代理商: MC33989
MC33989
25
MC33989
The wake-up inputs can be configured almost separetly, where L0 and L1 are configured together and L2 and L3 are
configured together.
Control bits:
.
Status bits:
note: Status bits have two functions. After SBC wake up, they indicate the wake up source (exemple: L2WU set at 1 if wake up
source is L2 input). After SBC wake and once the WUR has been read, status bits indicates the real time state of the Lx inputs (1
mean Lx is above threshold, 0 means that Lx input is below threshold).
If after a wake up from Lx input, a W/D timeout occurs before the first reading of the WUR register, the LxWU bits are reset.
This can occurs only if SBC was in stop mode.
7.1.6
TIM registers
Description: This register is splitted into 2 sub registers, TIM1 and TIM2.
TIM1 controls the watchdog timing selection as well as the window or time out option. TIM1 is selected when bit D3 is 0.
TIM2 is used to define the timing for the cyclic sense and forced wake up function. TIM2 is selected when bit D3 is 1.
No read operation is allowed for registers TIM1 and TIM2
Reset value
0
0
0
0
Reset condition
POR, NR2R, N2R, STB2R, STO2R
LCTR3
LCTR2
LCTR1
LCTR0
L0/L1 configuration
L2/L3 configuration
X
X
0
0
inputs disabled
X
X
0
1
high level sensitive
X
X
1
0
low level sensitive
X
X
1
1
both level sensitive
0
0
X
X
inputs disabled
0
1
X
X
high level sensitive
1
0
X
X
low level sensitive
1
1
X
X
both level sensitive
Status bit
Description
L3WU
Wake-up occurred (sleep/ stop mode), logic state on Lx
(standby/ normal mode)
L2WU
L1WU
L0WU
WUR
D3
D2
D1
D0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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