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參數(shù)資料
| 型號(hào)： | MC68HC05C5CFN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 10/58頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MC68HC05C5CFN |
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Page 12
MOTOROLA
Section 3: Memory
MC68HC05C5 Specification Rev. 1.2
following a delay of V
DD
/Slew rate.
When set, LVPI clears bits 0 through 6 in the
programming register to disable the charge pump and prevent programming.
CPEN cannot be set when LVPI is set. During reset, LVPI is set until V
DD
reaches V
LVPI
,
at which time it is cleared. The LVPI circuitry continues to function while the processor is
in STOP mode.
The LVPI function is a mask option. If this function is disabled, bit 7 will be set to a value
of "0".
3.3.1.2
CPEN - Charge Pump Enable
When set, CPEN enables the charge pump which produces the internal EEPROM
programming voltage. This bit should be set concurrently with the LATCH bit. The
programming voltage will not be available until EEPGM is set. The charge pump should
be disabled when not in use. This bit is automatically cleared by the LVPI circuit when
LVPI is set, and cannot be set until LVPI is cleared. CPEN is readable and writable and
is cleared by reset.
3.3.1.3
ER1:ER0 - Erase Select Bits
ER1 and ER0 form a 2-bit field which is used to select one of three erase modes: byte,
block, or bulk. Table 3-1 shows the modes selected for each bit configuration. These bits
are automatically cleared when LVPI is set. These bits are readable and writable and are
cleared by reset.
In byte erase mode, only the selected byte is erased. In block mode, a 32-byte block of
EEPROM is erased. The EEPROM memory space is divided into four 32-byte blocks
($100-$11F, $120-$13F, $140-$15F, $160-$17F), and doing a block erase to any address
within a block will erase the entire block.
In bulk erase mode, the entire 128-byte
EEPROM section is erased.
Table 3-1: Erase Mode Select
3.3.1.4
LATCH
When set, LATCH configures the EEPROM address and data bus for programming.
When LATCH is set, writes to the EEPROM array cause the data bus and the address
bus to be latched. This bit is readable and writable, but reads from the array are inhibited
if the LATCH bit is set and a write to the EEPROM space has taken place. When clear,
1
ER1
0
1
Bulk Erase
ER0
MODE
0
Program (no Erase)
1
Byte Erase
0
Block Erase
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