參數(shù)資料
型號(hào)： MC68HC05C5CFN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 36/58頁(yè)
文件大?。?/td> 166K
代理商： MC68HC05C5CFN
Page 35
Section 6: Timer
MOTOROLA
MC68HC05C5 Specification Rev. 1.2
After a processor write cycle to the output compare register containing the MSB ($16), the
output compare function is inhibited until the LSB ($17) is also written. The user must
write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17)
will not inhibit the compare function. The free-running counter is updated every four
internal bus clock cycles. The minimum time required to update the output compare
register is a function of the program rather than the internal hardware.
The processor can write to either byte of the output compare register without affecting the
other byte. The output level (OLVL) bit is clocked to the output level register regardless
of whether the output compare flag (OCF) is set or clear.
6.4
INPUT CAPTURE REGISTER
Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are
used to latch the value of the free-running counter after the corresponding input capture
edge detector senses a defined transition. The level transition which triggers the counter
transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the
contents of the input capture register except when exiting stop mode.
The result obtained by an input capture will be one more than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This
delay is required for internal synchronization. Resolution is one count of the free-running
counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on each
proper signal transition regardless of whether the input capture flag (ICF) is set or clear.
The input capture register always contains the free-running counter value that
corresponds to the most recent input capture.
After a read of the input capture register ($14) MSB, the counter transfer is inhibited until
the LSB ($15) is also read. This characteristic causes the time used in the input capture
software routine and its interaction with the main program to determine the minimum pulse
period.
A read of the input capture register LSB ($15) does not inhibit the free-running counter
transfer since they occur on opposite edges of the internal bus clock.
6.5
TIMER CONTROL REGISTER (TCR) $12
The TCR is a read/write register containing six control bits. Three bits control interrupts
associated with the timer status register flags ICF, OCF and TOF.
Figure 6-2: Timer Control Register
ICIE
TOIE
0
COE
IEDG
OLVL
OCIE
$12
0
0000
U
0
RESET:
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