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參數(shù)資料
| 型號： | MC68HC05C5CFN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 33/58頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MC68HC05C5CFN |
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Page 33
Section 6: Timer
MOTOROLA
MC68HC05C5 Specification Rev. 1.2
SECTION 6
TIMER
6.1
INTRODUCTION
The timer consists of a 16-bit, software-programmable counter driven by a fixed divide-
by-four prescaler. This timer can be used for many purposes, including input waveform
measurements while simultaneously generating an output waveform. Pulse widths can
vary from several microseconds to many seconds. Refer to Figure 6-1 for a timer block
diagram.
Because the timer has a 16-bit architecture, each specific functional segment (capability)
is represented by two registers. These registers contain the high and low byte of that
functional segment. Generally, accessing the low byte of a specific timer function allows
full control of that function; however, an access of the high byte inhibits that specific timer
function until the low byte is also accessed.
Note: The I bit in the CCR should be set while manipulating both the high and low byte
register of a specific timer function to ensure that an interrupt does not occur.
Input
Capture
Register
Clock
Internal Bus
Output
Compare
Register
High
Byte
Low
Byte
$16
$17
∏∏∏
/4
Internal
Processor
16-Bit Free
Running
Counter
Alternate
Register
8-Bit
Buffer
High
Byte
Low
Byte
$1A
$1B
$18
$19
High
Byte
Low
Byte
$14
$15
Output
Compare
Circuit
Overflow
Detect
Circuit
Edge
Detect
Circuit
Timer
Status
Reg.
ICF OCF TOF $13
ICIE
IEDG OLVL
Output
Level
Reg.
RESET
Timer
Control
Reg.
$12
Output
Level
(TCMP)
Interrupt
Circuit
TOIE
OCIE
Edge
Input
(TCAP)
D
CLK
C
Q
Figure 6-1: Timer Block Diagram
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