參數(shù)資料
型號: MC68HC05C5CFN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 41/58頁
文件大?。?/td> 166K
代理商: MC68HC05C5CFN
Page 40
MOTOROLA
Section 7: Simple Input/Output Port
MC68HC05C5 Specification Rev. 1.2
While the SIOP is enabled, PB5 can not be used as a standard output since that pin is
coupled to the last stage of the serial shift register. If CPOL is set, the first falling edge of
SCK will shift the first data bit out to the output pin. If CPOL is clear, the first data bit will
be on the SDO pin waiting for the transmission.
7.1.3
SDI
The SDI pin becomes an input as soon as the SIOP is enabled. New data may be
presented to the SDI pin on the falling edge of SCK. Valid data must be present at least
t
S
before the rising edge of the clock and remain valid for t
H
after the
edge.
Figure 7-2: Serial I/O Port Timing (CPOL=1)
Figure 7-3: Serial I/O Port Timing (CPOL=0)
7.2
SIOP REGISTERS
7.2.1
SIOP CONTROL REGISTER (SCR)
This register is located at address $000A and contains 3 bits.
SDO
BIT 1
BIT 2
BIT 3
BIT 7
SCK
BIT 8
SDI
BIT 1
BIT 2
BIT 3
BIT 7
BIT 8
SDO
BIT 1
BIT 2
BIT 3
BIT 7
SCK
BIT 8
SDI
BIT 1
BIT 2
BIT 3
BIT 7
BIT 8
0
MSTR
CPOL
0
SPE
$0A
0
001000
0
RESET:
Figure 7-4: SIOP Control Register
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