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參數(shù)資料
| 型號： | MC68HC05C5CFN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 19/58頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MC68HC05C5CFN |
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Page 20
MOTOROLA
Section 4: CPU Core
MC68HC05C5 Specification Rev. 1.2
4.2.4
BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any writable bit which resides in the first 256
bytes of the memory space where all port registers, port DDRs, timer, timer control, and
on-chip RAM reside. An additional feature allows the software to test and branch on the
state of any bit within these 256 locations. The bit set, bit clear and bit test and branch
functions are all implemented with a single instruction. For test and branch instructions,
the value of the bit tested is also placed in the carry bit of the condition code register.
These instructions are also read-modify-write instructions. Do not bit manipulate write-
only locations. Refer to the following list for bit manipulation instructions.
4.2.5
CONTROL INSTRUCTIONS
These instructions are register reference instructions and are used to control processor
operation during program execution. Refer to the following list for control instructions.
Function
Branch if Bit n is Set
Branch if Bit n is Clear
Set Bit n
Clear Bit n
Mnemonic
BRSET n (n = 0. . .7)
BRCLR n (n = 0. . .7)
BSET n (n = 0. . .7)
BCLR n (n = 0. . .7)
Function
Transfer A to X
Transfer X to A
Set Carry Bit
Clear Carry Bit
Mnemonic
TAX
TXA
SEC
CLC
Set Interrupt Mask Bit
SEI
Clear Interrupt Mask Bit
CLI
Software Interrupt
SWI
Return from Subroutine
RTS
Return from Interrupt
RTI
Reset Stack Pointer
RSP
No-Operation
NOP
Wait
WAIT
Stop
STOP
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