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參數(shù)資料
| 型號： | MC68HC05C5CFN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 43/58頁 |
| 文件大小： | 166K |
| 代理商： | MC68HC05C5CFN |
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Page 42
MOTOROLA
Section 7: Simple Input/Output Port
MC68HC05C5 Specification Rev. 1.2
STASCRset SPE
7.2.2
SIOP STATUS REGISTER (SSR)
This register is located at address $000B and contains only 2 bits.
7.2.2.1
SPIF - SERIAL PERIPHERAL INTERFACE FLAG
This bit is set upon occurrence of the last rising clock edge if CPOL is set and the last
falling clock edge of CPOL is clear to indicates that a data transfer has taken place. It
has no effect on any further transmissions and can be ignored without problem. SPIF is
cleared by reading the SSR with SPIF set followed by a read or write of the serial data
register. If SPIF is cleared before the last edge of the next byte, it will be set again. Reset
clears this bit.
7.2.2.2
DCOL - DATA COLLISION
This is a read-only status bit which indicates that an invalid access to the data register has
been made. This can occur any time after the first falling edge of SCK if CPOL is set and
after the first rising edge of SCK if CPOL is clear and before SPIF is set. A read or write
of the data register during this time will result in invalid data being transmitted or received.
DCOL is cleared by reading the status register with SPIF set followed by a read or write
of the data register.
If the last part of the clearing sequence is done after another
transmission has been started, DCOL will be set again. Reset also clears this bit.
7.2.3
SIOP DATA REGISTER (SDR)
This register is located at address $000C and is both the transmit and receive data
register. This system is not double buffered and any write to this register will destroy the
previous contents. The SDR can be read at any time, but if a transmission is in progress
the results may be ambiguous. Writes to the SDR while a transmission is in progress can
cause invalid data to be transmitted and/or received. This register can be read and written
only when the SIOP is enabled (SPE=1).
SPIF
000000
DCOL
$0B
0
000000
0
RESET:
Figure 7-5: SIOP Status Register
$0C
U
UUUUUU
U
RESET:
Figure 7-6: SIOP Data Register
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