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參數(shù)資料
| 型號(hào)： | MC68HC05L1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 16/102頁 |
| 文件大?。?/td> | 632K |
| 代理商： | MC68HC05L1B |
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MOTOROLA
2-2
MC68HC05L1
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
2
PC0-PC7
AN0-AN5
VRH, VRL
37-44
37-42
43, 44
35-42
35-40
41, 42
These eight lines comprise port C. These port lines perform either as
standard input ports or as ADC inputs.
AN0-AN5 are the ADC input channels. VRH and VRL are the ADC
voltage reference inputs.
Port C is congured for ADC use when the ADON bit in the ADC
Status/Control register (bit 5 of address $09) is set.
PD0-PD3
TCAP1, TCAP2
TCMP1, TCMP2
16, 15, 13, 14
16, 15
13, 14
10, 9, 7, 8
10, 9
7, 8
These four lines comprise port D. PD0 and PD1 are input only and are
shared with TCAP1 and TCAP2. PD2 and PD3 are output only and
are shared with TCMP1 and TCMP2. TCAPx and TCMPx are
functions of the programmable timer.
PD2/TCMP1 is set for TCMP1 when the TE2 bit is “0” in the General
Control register ($0A).
PD3/TCMP2 is set for TCMP2 when the TE1 bit is “0” in the General
Control register ($0A).
PE0
17
11
Port E consist of only one pin. The state of this pin is software
programmable, and is congured as input during power on or external
reset.
VBP0-VBP3
12, 11, 10, 9
6, 5, 4, 3
These 4 output pins provide the backplane drive signals to the LCD
unit. If a 3x multiplex is selected, VBP3 should be grounded.
VSEG0-VSEG15
8-1, 56-49
1, 2, 62-51,
48, 47
These 16 output pins provide the segment drive signals to the LCD
unit. If only x12 multiplex is selected, VSEG12-VSEG15 should be
grounded.
VLCD
48
46
This pin is the input voltage to the LCD driver circuitry.
PIN NAME
56-pin SDIP
PIN No.
64-pin QFP
PIN No.
DESCRIPTION
TPG
18
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