參數(shù)資料
型號： MC68HC05L1B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： SDIP-56
文件頁數(shù)： 45/102頁
文件大?。?/td> 632K
代理商： MC68HC05L1B
MC68HC05L1
MOTOROLA
5-11
PROGRAMMABLE TIMER
5
1 (set)
–
Timer Overow has occurred.
0 (clear) –
No timer overow has occurred.
When using the timer overow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overow ag is unintentionally
cleared if:
1) the Timer Status register is read or written when the TOF is set, and
2) the LSB of the free-running counter is read, but not for the purpose of
servicing the ag.
Reading the Alternate Counter register instead of the Counter register will avoid this potential
problem.
ICF2 - Input Capture Flag 2
This bit is set when a negative edge is detected by the input capture edge detector 2 at TCAP2;
an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by reading the TSR and
then the Input Capture Low register 2 ($1D).
1 (set)
–
A valid input capture has occurred at TCAP2 pin.
0 (clear) –
No input capture has occurred at TCAP2 pin.
OCF2 - Output Compare Flag 2
This bit is set when the Output Compare 2 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF2 is cleared by reading
the TSR and then the Output Compare 2 Low register ($1F).
1 (set)
–
A valid output compare has occurred on output compare register 2.
0 (clear) –
No output compare has occurred on output compare register 2.
5.5
Programmable Timer Timing Diagrams
The relationships between the internal clock signals, the counter contents and the status of the
ag bits are shown in the following diagrams. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and reset) are not available to the user.
TPG
45
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