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參數(shù)資料
| 型號： | MC68HC05L1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 31/102頁 |
| 文件大?。?/td> | 632K |
| 代理商： | MC68HC05L1B |
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MOTOROLA
4-6
MC68HC05L1
RESETS AND INTERRUPTS
4
4.2.3
External Interrupt (IRQ)
The external interrupt IRQ can be software congured for “negative-edge” or “negative-edge and
level” sensitive triggering by the INTO bit in the General Control register.
INTO
1 (set)
–
Negative edge triggering for IRQ only.
0 (clear) –
Level and negative edge triggering for IRQ.
When the signal of the external interrupt pin, IRQ, satises the condition selected, an external
interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared. When the interrupt is recognized, the current state of the
processor is pushed onto the stack and the interrupt mask bit in the condition code register is set.
This masks further interrupts until the present one is serviced. The service routine address is
specied by the contents of $1FFA & $1FFB.
The interrupt logic recognizes negative edge transitions and pulses (special case of negative
edges) on the external interrupt line. Figure 4-4 shows both a block diagram and timing for the
interrupt line (IRQ) to the processor. The rst method is used if pulses on the interrupt line are
spaced far enough apart to be serviced. The minimum time between pulses is equal to the number
of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the
next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The
second conguration shows several interrupt lines wired-OR to perform the interrupt at the
processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is
recognized.
Note:
The internal interrupt latch is cleared in the rst part of the service routine; therefore,
one (and only one) external interrupt pulse could be latched during tILIL and serviced
as soon as the I bit is cleared.
4.2.4
Programmable Timer Interrupt
Five timer interrupt ags are found in the ve most signicant bits of the Timer Status register
(TSR) at location $13. All ve interrupts will vector to their respective addresses as indicated in
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
General Control Register
$0A
INTO
TE2
TE1
DON
INT
MS
0000 0000
TPG
32
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