參數(shù)資料
型號(hào)： MC68HC05L1B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： SDIP-56
文件頁(yè)數(shù)： 44/102頁(yè)
文件大?。?/td> 632K
代理商： MC68HC05L1B
MOTOROLA
5-10
MC68HC05L1
PROGRAMMABLE TIMER
5
OLVL1 - Output Level Voltage Latch 1
When OLVL1 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level
which will appear on the TCMP1 pin.
1 (set)
–
High output on TCMP1 pin if counter compare 1 is true.
0 (clear) –
Low output on TCMP1 pin if counter compare 1 is true.
5.4.2
Timer Status Register (TSR)
The Timer Status register ($13) contains the status bits corresponding to the four timer interrupt
conditions - ICF1, OCF1, TOF, ICF2 and OCF2.
Accessing the Timer Status register satises the rst condition required to clear the status bits.
The remaining step is to access the register corresponding to the status bit.
ICF1 - Input Capture Flag 1
This bit is set when the selected polarity of the edge is detected by the input capture edge detector
1 at TCAP1; an input capture interrupt will be generated if ICIE is set. ICF1 is cleared by reading
the TSR and then the Input Capture Low register 1 ($15).
1 (set)
–
A valid input capture has occurred at TCAP1 pin.
0 (clear) –
No input capture has occurred at TCAP1 pin.
OCF1 - Output Compare Flag 1
This bit is set when the output compare 1 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF1 is cleared by reading
the TSR and then the Output Compare 1 Low register ($17).
1 (set)
–
A valid output compare has occurred on output compare register 1.
0 (clear) –
No output compare has occurred on output compare register 1.
TOF - Timer Overow Flag
This bit is set when the free-running counter overows from $FFFF to $0000; a timer overow
interrupt will occur if TOIE is set. TOF is cleared by reading the TSR and the Counter Low register
($19).
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer status (TSR)
$0013
ICF1
OCF1
TOF
ICF2
OCF2
uuuu u000
TPG
44
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