參數(shù)資料
型號(hào)： MC68HC05L1B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： SDIP-56
文件頁數(shù)： 33/102頁
文件大?。?/td> 632K
代理商： MC68HC05L1B
MOTOROLA
4-8
MC68HC05L1
RESETS AND INTERRUPTS
4
Each flag bit is defined as follows:
TOF - Timer Overow Flag
TOF is set during the counter transition of $FFFF to $0000. It is cleared by
reading the TSR (with TOF set) followed by reading the Counter Low register
($19).
OCF1, OCF2 - Output Compare Flag 1 and Output Compare 2
The appropriate OCF is set when the corresponding Output Compare register
matches the Counter register. It is cleared by reading the TSR (with OCF set)
and then accessing the corresponding Output Compare Low register ($17 or
$1F).
ICF1, ICF2 - Input Capture Flag
The appropriate ICF is set when a proper edge has been sensed by the input
capture edge detector. It is cleared by an CPU read of the TSR (with ICF set) and
then accessing the corresponding Input Capture Low register ($15 or $1D).
There are three timer interrupt enable bits (TOIE, OCIE, and ICIE) in the Timer Control register
(TCR) at location $12, which controls these interrupt ags. Reset clears all enable bits preventing
an interrupt from occurring. The actual processor interrupt is generated only if the interrupt mask
bit of the condition code register is also cleared. When the interrupt is recognized, the current state
of the machine is pushed onto the stack and the interrupt mask bit in the condition code register
is set. This masks further interrupts until the present one is serviced. The service routine address
is specied by the contents of the respective vectors; see Table 4-2.
Refer to section 5 for detailed description of Programmable Timer.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer Status Register
$13
ICF1
OCF1
TOF
ICF2
OCF2
uuuu u000
TPG
34
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