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| 型號： | MC8610TVT1066JB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 13/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU E600 CORE 1066MHZ 783-PBGA |
| 標準包裝： | 36 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.066GHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
20
Figure 3 illustrates the power up sequence as described above.
Figure 3. MPC8610 Power Up Sequencing
VDD_PLAT, AVDD_PLAT
OVDD
Time
2.5 V
3.3 V
0
DC
P
o
w
e
rSupp
ly
V
o
lt
age
Reset
Configuration Pins
HRESET (& TRST)
Asserted for
100
μs4
VDD Stable
Power Supply Ramp Up 2
Notes:
1. Dotted waveforms correspond to optional supply values for a specified power supply. See Table 3.
2. Ther recommended maximum ramp up time for power supplies is 20 milliseconds.
3. Refer to Section 2.5, “RESET Initialization” for additional information on PLL relock and reset signal
assertion timing requirements.
4. Refer to Table 9 for additional information on reset configuration pin setup timing requirements. In
addition see Figure 53 regarding HRESET and JTAG connection details including TRST.
5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles.
6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration
inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles
after HRESET has negated (hold requirement). See Section 2.5, “RESET Initialization,” for more
information on setup and hold time of reset configuration signals.
7. The rail for VDD_PLAT, AVDD_PLAT, VDD_Core, AVDD_Core, AVDD_PCI, SnVDD, XnVDD, and SDnAVDD
must reach 90% of its value before the rail for GVDD and MVREF reaches 10% of its value.
8. SYSCLK must be driven only AFTER the power for the various power supplies is stable.
9. The reset configuration signals for DRAM types must be valid before HRESET is asserted.
e6005
AVDD_PCI, SnVDD, XnVDD
VDD_Core, AVDD_Core
SD
nAVDD
1.8 V
GVDD, = 1.8/2.5 V
MVRE
F
SYSCLK8 (not drawn to scale)
7
PLL
9
Cycles Setup and Hold Time 6
100 s Platform PLL
Relock Time3
1.0 V
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| MC8610PX1066JB | MPU E600 CORE 1066MHZ 783-PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MC8610TVT1066JZ | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8610 Integrated Host Processor Hardware Specifications |
| MC8610TVT1067G | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8610TVT1067J | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8610TVT1333JB | 制造商:Freescale Semiconductor 功能描述:MPC8XXX RISC 32-BIT 0.09UM 1.333GHZ 1.8V/2.5V/3.3V 783-PIN B - Bulk |
| MC8610TVT667FB | 功能描述:微處理器 - MPU REV 1.1 8610 1.0V -40C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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