參數(shù)資料
型號： MC8610TVT1066JB
廠商： Freescale Semiconductor
文件頁數(shù)： 38/96頁
文件大?。?/td> 0K
描述： MPU E600 CORE 1066MHZ 783-PBGA
標準包裝： 36
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.066GHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
43
2.12.2
SSI AC Timing Specifications
All timings for the SSI are given for a noninverted serial clock polarity (TSCKP/RSCKP = 0) and a noninverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the following tables and figures.
For internal frame sync operation using external clock, the FS timing will be same as that of Tx Data.
2.12.2.1
SSI Transmitter Timing with Internal Clock
Table 35 provides the transmitter timing parameters with internal clock.
Table 34. SSI DC Electrical Characteristics (3.3 V DC)
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2BVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current (BVIN
1 = 0 V or BV
IN = BVDD)IIN
—±5
μA
High-level output voltage (BVDD = min, IOH = –2 mA)
VOH
BVDD – 0.2
—
V
Low-level output voltage (BVDD = min, IOL = 2 mA)
VOL
—0.2
V
Note:
1. The symbol BVIN, in this case, represents the BVIN symbol referenced in Table 2 and Table 3.
Table 35. SSI Transmitter with Internal Clock Timing Parameters
Parameter
Symbol
Min
Max
Unit
Internal Clock Operation
(Tx/Rx) CK clock period
SS1
81.4
—
ns
(Tx/Rx) CK clock high period
SS2
36.0
—
ns
(Tx/Rx) CK clock rise time
SS3
—
6
ns
(Tx/Rx) CK clock low period
SS4
36.0
—
ns
(Tx/Rx) CK clock fall time
SS5
—
6
ns
(Tx) CK high to FS high
SS10
—
15.0
ns
(Tx) CK high to FS low
SS12
—
15.0
ns
(Tx/Rx) internal FS rise time
SS14
—
6
ns
(Tx/Rx) internal FS fall time
SS15
—
6
ns
(Tx) CK high to STXD valid from high impedance
SS16
—
15.0
ns
(Tx) CK high to STXD high/low
SS17
—
15.0
ns
(Tx) CK high to STXD high impedance
SS18
—
15.0
ns
STXD rise/fall time
SS19
—
6
ns
Synchronous Internal Clock Operation
SRXD setup before (Tx) CK falling
SS42
10.0
—
ns
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