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| 型號： | MC92600 |
| 廠商： | Motorola, Inc. |
| 英文描述： | High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口) |
| 中文描述： | 高速，全雙工，串行數(shù)據(jù)接口（高速全雙工串行數(shù)據(jù)接口） |
| 文件頁數(shù)： | 27/82頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | MC92600 |
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Chapter 3. WarpLink Receiver
3-5
Alignment Modes
alignment with idle realignment and disparity-based word alignment, and non-aligned data.
3.3.1.1 Byte-Aligned with Realignment
At power-up, the receiver starts an alignment procedure, searching for the 10-bit pattern
deTned by the 8B/10B idle code. Synchronization logic checks for the distinct idle
sequence, 0011111010 and 1100000101 (ordered bit 0 to bit 9), characteristic of the
K28.5 idle pattern. The search is done on the 10-bit data in the receiver, and is therefore
independent of TBI mode. Alignment requires a minimum of four, error-free, received idle
characters to ensure proper alignment and lock. Non-idle characters may be interspersed
with the idle characters. The disparity of the idle characters is not important to alignment
and can be positive, negative or any combination. The receiver begins to forward received
characters once locked on an alignment. However, if word synchronization is enabled
(WSE = high), received characters are not forwarded to the receiver interface until the
Trst, valid, non-idle character is received. Alignment remains locked until one of three
events occurs that indicate loss of alignment:
￥
Alignment is lost when a misaligned idle sequence is detected. A misaligned idle
sequence is deTned as four idle characters with an alignment different from the
current alignment. Non-idle characters may be dispersed between the four
misaligned idles, however, a properly aligned idle character breaks the sequence.
Alignment is changed to the newly detected alignment without interrupting data
ow through the receiver.
￥
Alignment is also lost when the number of received characters with 8B/10B coding
errors outnumbers the non-errored characters by four. Misalignment detection of
this type is not available in TBI mode. The receiver restarts its alignment procedure
and halts data ow until alignment is achieved.
￥
Finally, the user may force loss of alignment by asserting WSE_GEN high and
XMIT_n_K low on all four receivers simultaneously. The receiver restarts its
alignment procedure and halts data ow until alignment is achieved.
When establishing byte alignment, or when data ow is halted due to misalignment, the
receivers RECV_n_ERR signal is asserted high and the òNot Byte Syncó error is reported
as described in Section 3.7, òReceiver Interface Error Codes.ó
Table 3-2. Byte Alignment Modes
Byte Alignment Mode
BSYNC_0
BSYNC_1
Byte aligned with realignment
Low
Low
Byte aligned with fast alignment/realignment
Low
High
Byte aligned with idle realignment and disparity word
alignment
High
Low
Non-aligned
High
High
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