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| 型號： | MC92600 |
| 廠商： | Motorola, Inc. |
| 英文描述： | High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口) |
| 中文描述： | 高速，全雙工，串行數(shù)據(jù)接口（高速全雙工串行數(shù)據(jù)接口） |
| 文件頁數(shù)： | 33/82頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | MC92600 |
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Chapter 3. WarpLink Receiver
3-11
Device Operations
The input ampliTers electrical speciTcations may be found in Table 6-3ó and in Table 6-4,
"DC Electrical SpeciTcations for 2.5V Power Supply.ó
3.5.2 8B/10B Decoder Operation
The 8B/10B decoder takes the 10-bit character from the transition tracking loop and
decodes it according to the 8B/10B coding standard [1,2]. The decoder does two types of
error checking. First it checks that all characters are a legal member of the 8B/10B coding
space. The decoder also checks for running disparity errors. If the running disparity exceeds
the limits set in the 8B/10B coding standard then a disparity error is generated. See
Appendix 0, ò8B/10B Coding Scheme.ó
An illegal character or disparity error sets the RECV_n_ERR signal high, coincident with
the received data for a 1-byte output period. The òCode Erroró or òDisparity Erroró is
reported as described in Section 3.7, òReceiver Interface Error Codes.ó It is difTcult to
determine the exact byte that caused the disparity error, so it should not be associated with
a particular received byte. It is rather a general indicator of the improper operation of the
link. Its intended use is for the system to monitor link reliability.
The 8B/10B decoder is bypassed when operating in 10-bit interface mode (TBIE = high.)
3.5.3 Transition Tracking Loop and Data Recovery
The received differential data from the input ampliTer is sent to the transition tracking loop
for data recovery. The WarpLink Quad uses a 16X oversampled transition tracking loop
method for data recovery. A key element in this methodology is the delay line.
The differential delay line provides 16 samples of data per bit-time, enabling bit-time
synchronization and data recovery. The delay line is tunable for two operating ranges, 1
Gbps and 500 Mbps, with allowances made for process, voltage and temperature (PVT)
variation and reference frequency range. Operating range is determined by the state of the
half-speed enable (HSE) input. HSE set low establishes 1 Gbps operation, and HSE high
enables 500 Mbps range.
The receiver operates using the transceiver clock, rx_clock, which is generated by the
integrated PLL. rx_clock runs at 625 MHz for 1 Gbps (1.25 gigabaud) operation and at
312.5 MHz for 500 Mbps (625 megabaud) operation. Delay line samples are processed
twice per rx_clock period giving baud rate equal to two times rx_clock frequency.
The WarpLink Quad is tolerant of frequency offset between the transmitter and receiver.
WarpLink reliably operates with +250 ppm of frequency offset. The devices transition
tracking loop method is different than the typical PLL clock recovery method. Its receiver
compensates for overrun and underrun caused by frequency offset by modulating the
duty-cycle and period of the received byte clock.
Recovered data is accumulated into 10-bit characters. Characters are aligned to their
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