參數(shù)資料
型號: MC92600
廠商: Motorola, Inc.
英文描述: High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口)
中文描述: 高速,全雙工,串行數(shù)據(jù)接口(高速全雙工串行數(shù)據(jù)接口)
文件頁數(shù): 57/82頁
文件大?。?/td> 1056K
代理商: MC92600
Chapter 6. Electrical SpeciTcations and Characteristics
6-11
Electrical Characteristics
6.1.4 Power Supply Requirements
The board design should have a minimum of two solid planes of one ounce copper. One
plane is to be used as a ground plane and the second plane is to be used for the 1.8V supply.
It is recommended that the board has its own 1.8V and 3.3V regulators with less than 0.1%
ripple.
6.1.5 Phase-Locked Loop (PLL) Power Supply Filtering
An analog power supply is required for the internal PLL. The PLLAVDD signal provides
power for the analog portions of the PLL. To ensure stability of the internal clock, the power
supplied to the PLL is Tltered using a circuit similar to the one shown in Figure 6-11. For
maximum effectiveness, the Tlter circuit is placed as close as possible to the PLLAVDD
ball to ensure it Tlters out as much noise as possible. The ground connection should be near
the PLLAGND ball. The 0.003
m
F capacitor is closest to the ball, followed by the 0.3
m
F
capacitor, and Tnally the 3
W
resistor to Vdd on the 1.8V power plane. The capacitors are
connected from PLLAVDD to the ground plane. Use ceramic chip capacitors with the
highest possible self-resonant frequency. All traces should be kept short, wide and direct.
Figure 6-11. PLL Power Supply Filter Circuit
6.1.6 Decoupling Recommendations
The WarpLink Quad requires a clean, tightly regulated source of power to ensure low jitter
on transmit, and reliable recovery of data in the receiver. Recommendations for appropriate
decoupling are outlined below.
Only surface mount technology (SMT) capacitors should be used, to minimize
inductance. Connections from all capacitors to power and ground should be done
with multiple vias to further reduce inductance.
The board should have about 10 x 10nF SMT ceramic chip capacitors as close as
possible to the 1.8V (Vdd and XVdd) balls of the device. The board should also have
about 10 x 10nF SMT ceramic chip capacitors as close as possible to the 3.3V
(OVdd) balls of the device. Where the board has blind vias, these capacitors should
be placed directly below the WarpLink Quad supply and ground connections. Where
the board does not have blind vias, these capacitors should be placed in a ring around
the WarpLink Quad, as close to the supply and ground connections as possible.
VDD
3
W
0.003 μF
PLLAVDD
0.3 μF
GND
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