參數(shù)資料
型號(hào): MC92600
廠商: Motorola, Inc.
英文描述: High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口)
中文描述: 高速,全雙工,串行數(shù)據(jù)接口(高速全雙工串行數(shù)據(jù)接口)
文件頁(yè)數(shù): 66/82頁(yè)
文件大?。?/td> 1056K
代理商: MC92600
6-20
MC92600 WarpLink Quad Users Manual
WarpLink Quad Chip Pinout Listing
RECV_A_2
Receiver A, data bit 2
M2
T1
Output
TTL
RECV_A_3
Receiver A, data bit 3
N2
P3
Output
TTL
RECV_A_4
Receiver A, data bit 4
P1
N4
Output
TTL
RECV_A_5
Receiver A, data bit 5
M5
R3
Output
TTL
RECV_A_6
Receiver A, data bit 6
M3
T2
Output
TTL
RECV_A_7
Receiver A, data bit 7
M4
T3
Output
TTL
RECV_A_K
Receiver A, special character
(data bit 8 for TBI mode)
P2
U3
Output
TTL
RECV_A_9
Receiver A, data bit 9 for TBI
mode
N3
T4
Output
TTL
RECV_A_IDLE
Receiver A, idle detect
L5
R4
Output
TTL
RECV_A_ERR
Receiver A, error detect
P4
R5
Output
TTL
RECV_A_RCLK
Receiver A, receive data clock
P3
U4
Output
TTL
RLINK_A_P
Receiver A, positive link input
L14
N17
Input
Link
RLINK_A_N
Receiver A, negative link input
M14
P17
Input
Link
XLINK_A_P
Transmitter A, positive link out
K12
M15
Output
Link
XLINK_A_N
Transmitter A, negative link out
L12
N15
Output
Link
XMIT_B_0
Transmitter B, data bit 0
P7
R8
Input
TTL
XMIT_B_1
Transmitter B, data bit 1
N7
T8
Input
TTL
XMIT_B_2
Transmitter B, data bit 2
L7
R7
Input
TTL
XMIT_B_3
Transmitter B, data bit 3
M7
U7
Input
TTL
XMIT_B_4
Transmitter B, data bit 4
P6
T7
Input
TTL
XMIT_B_5
Transmitter B, data bit 5
N6
U6
Input
TTL
XMIT_B_6
Transmitter B, data bit 6
P5
R6
Input
TTL
XMIT_B_7
Transmitter B, data bit 7
L6
T6
Input
TTL
XMIT_B_K
Transmitter B, special character
(data bit 8 for TBI mode)
M6
U5
Input
TTL
XMIT_B_IDLE_B
Transmitter B, idle enable bar,
(data bit 9 for TBI mode)
N5
T5
Input
TTL
RECV_B_0
Receiver B, data bit 0
K3
P2
Output
TTL
RECV_B_1
Receiver B, data bit 1
L4
P1
Output
TTL
RECV_B_2
Receiver B, data bit 2
L1
M3
Output
TTL
RECV_B_3
Receiver B, data bit 3
J3
N1
Output
TTL
RECV_B_4
Receiver B, data bit 4
K4
M2
Output
TTL
RECV_B_5
Receiver B, data bit 5
K2
L3
Output
TTL
RECV_B_6
Receiver B, data bit 6
K1
M1
Output
TTL
RECV_B_7
Receiver B, data bit 7
H3
L2
Output
TTL
Table 6-16. WarpLink Quad Chip Pinout List (Continued)
Signal Name
Description
Ball Number
(196 FBGA)
Ball Number
(217 PBGA)
Direction
I/O Type
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