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參數(shù)資料
| 型號(hào)： | MCZ33989EG |
| 廠(chǎng)商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類(lèi)： | CAN |
| 英文描述： | System Basis Chip with High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片高高速CAN收發(fā)器 |
| 文件頁(yè)數(shù)： | 26/66頁(yè) |
| 文件大?。?/td> | 1181K |
| 代理商： | MCZ33989EG |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
26
33989
FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
DEVICE POWER-UP, SBC WAKE-UP
After device or system power-up, or after the SBC wakes
up from Sleep mode, it enters into Reset mode prior to
moving into Normal Request mode.
DEBUG MODE: HARDWARE AND SOFTWARE
DEBUG WITH THE SBC
When the SBC is mounted on the same printed circuit
board as the microcontroller it supplies, both application
software and SBC dedicated routine must be debugged. The
following features allow debug of the software by allowing the
possibility of disabling the SBC internal software Watchdog
timer.
DEVICE POWER-UP, RESET PIN CONNECTED TO
VDD1
At SBC power-up the V
DD1
voltage is provided, but if no
SPI communication occurs to configure the device, a reset
occurs every 350 ms. In order to allow software debug and
avoid MCU reset, the Reset pin can be connected directly to
VDD1 by a jumper.
DEBUG MODES WITH SOFTWARE WATCHDOG
DISABLED THOUGH SPI (NORMAL DEBUG,
STANDBY AND STOP DEBUG)
The Watchdog software can be disabled through SPI. To
avoid unwanted watchdog disable while limiting the risk of
disabling Watchdog during SBC normal operation, the
watchdog disable must be achieved the following sequence:
Step 1–Power down the SBC
Step 2–Power-up the SBC (The BATFAIL bit is set,
allowing the SBC to enter Normal Request mode)
Step 3–Write to TIM1 register allowing SBC entering
Normal mode
Step 4–Write to MCR register with data 0000, enabling the
Debug mode. Complete SPI byte: 000 1 0000
Step 5–Write to MCR register normal debug (0001x101)
Step 6–To leave the Debug mode, write 0000 to MCR
register
While in Debug mode, the SBC can be used without
having to clear the WD on a regular basis to facilitate
software and hardware debug.
At Step 2, the SBC is in Normal Request. Steps 3, 4, and
5 should be completed consecutively and within the 350 ms
time period of the Normal Request mode. If this step is not
accomplished in a timely manner, the SBC will go into Reset
mode, entering Normal Request again.
When the SBC is in Debug mode, and set in Stop Debug
or Sleep Debug, when a wake-up occurs the SBC enters
Normal Request mode for a time period of 350 ms. To avoid
the SBC generating a reset (enter Reset mode) the desired
next Debug mode (Normal Debug or Standby Debug) should
be configured within the 350 ms time period of the Normal
Request mode. For details, please refer to State Machine in
Debug mode,
Figure 16
.
To avoid entering Debug mode after a power-up, first read
BATFAIL bit (MCR read) and write 0000 into MCR.
Figure 15
illustrates the Debug mode enter.
Figure 11. Debug Mode Enter
MCU FLASH PROGRAMMING CONFIGURATION
To download software into the application memory (MCU
EEPROM or Flash) the SBC capabilities allows the V
DD1
to
be forced by an external power supply to 5.0 V; the reset and
WD outputs by external signal sources are forced to zero or
5.0 V, both without damage. This allows, for example, supply
of the complete application board by external power supply,
applying the correct signal to reset pins. No function of the
SBC is operating.
Due to pass transistor from VDD1 to VSUP, supplying the
device from VDD1 pin biases the VSUP pin. Therefore, V
SUP
should not be forced to a value above 5.0 V. The Reset pin is
periodically pulled low for RST
DUR
time (3.4 ms typical)
before being pulled to V
DD1
for 350 ms typical. During the
time reset is low, the reset pin sinks 5.0 mA maximum (L
PDW
parameter).
VSUP
SPI
MCR(Step4)
Batfail
VDD1
Debug Mode
MCR (Step5)
SPI: Read Batfail
MCR (Step6)
SBC in Debug Mode, No WD
SBC Not in Debug Mode and WD ON
TIM1(Step 3)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCZ33989EG | 制造商:Freescale Semiconductor 功能描述:IC SYSTEM BASIS W/CAN TRANCEIVER |
| MCZ33989EGR2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-HS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCZ33990EF | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC CLASS B SERIAL TRANS. RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCZ33990EF | 制造商:Freescale Semiconductor 功能描述:TRANCEIVER J-1850 CLASS B 8SOIC |
| MCZ33990EF/R2 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Enhanced Class B Serial Transceiver |
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