參數(shù)資料
型號(hào): MCZ33989EG
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類: CAN
英文描述: System Basis Chip with High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片高高速CAN收發(fā)器
文件頁(yè)數(shù): 31/66頁(yè)
文件大?。?/td> 1181K
代理商: MCZ33989EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Mode Control Register (MCR)
Table 9
provides Mode Control Register data.
Table 9. MCR Register
MCR
D3
D2
D1
D0
$000B
W
MCTR2
MCTR1
MCTR0
R
BATFAIL
(31)
VDDTEMP
GFAIL
WDRST
Reset Value
0
0
0
Reset Condition
POR, RESET
POR, RESET
POR, RESET
Notes
31.
Bit BATFAIL cannot be set by SPI. BATFAIL is set when V
SUP
falls below 3.0 V.
Table 10. MCR Control Bits
MCTR2
MCTR1
MCTR0
SBC Mode
Description
0
0
0
Enter/Exit Debug Mode
To enter/exit Debug Mode, refer to detail
Debug Mode: Hardware and Software Debug...
0
0
1
Normal
0
1
0
Standby
0
1
1
Stop, Watchdog OFF
(32)
0
1
1
Stop, Watchdog ON
(32)
1
0
0
Sleep
(33)
1
0
1
Normal
No watchdog running, Debug Mode
1
1
0
Standby
1
1
1
Stop
Notes
32.
33.
Watchdog ON or OFF depends on RCR bit D3.
Before entering Sleep mode, bit BATFAIL in MCR must be previously cleared (MCR read operation), and bit NOSTOP in RCR must be
previously set to 1.
Table 11. MCR Status Bits
Status Bits
Description
GFAIL
Logic OR of CAN Failure (TXF Permanent Dominant, or CAN Over Current or CAN thermal), or HS1 Over
Temperature, or V2 Low
BATFAIL
Battery Fail Flag (set when V
SUP
< 3.0 V)
VDDTEMP
Temperature Pre-Warning on V
DD
(latched)
WDRST
Watchdog Reset Occurred
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