參數(shù)資料
型號: MCZ33989EG
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip with High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片高高速CAN收發(fā)器
文件頁數(shù): 35/66頁
文件大?。?/td> 1181K
代理商: MCZ33989EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Timing Register (TIM1/2)
This register is composed of two registers:
1. TIM1–controls the watchdog timing selection as well as
the window or timeout option. TIM1 is selected when
bit D3 is 0. Please see
Table 24
.
2. TIM2–is used to define the timing for the cyclic sense
and forced wake-up function. TIM2 is selected when bit
D3 is read operation it is not allowed in either TIM1 or
TIM2 registers. Please see
Table 26
.
Figure 17. Window Watchdog
Figure 18. Timeout Watchdog
Table 24. TIM1 Register
TMI1
D3
D2
D1
D0
$101B
W
0
WDW
WDT1
WDT0
R
Reset Value
0
0
0
Reset Condition
POR, RST
POR, RST
POR, RST
Table 25. TIM1 Control Bits
WDW
WDT1
WDT0
Timing (ms)
Parameter
0
0
0
10
Watchdog Period 1
No Window Watchdog
0
0
1
45
Watchdog Period 2
0
1
0
100
Watchdog Period 3
0
1
1
350
Watchdog Period 4
1
0
0
10
Watchdog Period 1
Window Watchdog Enabled (Window
Length is Half the Watchdog Timing)
1
0
1
45
Watchdog Period 2
1
1
0
100
Watchdog Period 3
1
1
1
350
Watchdog Period 4
WD Timing x 50%
WD Timing x 50%
Watchdog Period
(WD Timing Selected by TIM1 Bit WDW=1)
Window Open
for Watchdog Clear
Watchdog Period
(WD Timing Selected by TIM1 Bit WDW=1)
Table 26. TIM2 Register
TMI2
D3
D2
D1
D0
$101B
W
1
CSP2
CSP1
CSP0
R
Reset Value
0
0
0
Reset Condition
POR, RST
POR, RST
POR, RST
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