參數(shù)資料
型號: MCZ33989EG
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip with High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片高高速CAN收發(fā)器
文件頁數(shù): 36/66頁
文件大?。?/td> 1181K
代理商: MCZ33989EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
36
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 19. HS1 Operation when Cyclic Sense is Selected
Low Power Mode Control Register (LPC)
This register controls:
The state of HS1 in Stop and Sleep mode (HS1
permanently off or HS1 cyclic)
Enable or disable the forced wake-up function (SBC
automatic wake-up after time spend in Sleep or Stop
modes, time is defined by the TIM2 register)
Enable or disable the sense of the wake-up inputs (Lx) at
sampling point of the Cyclic Sense period (LX2HS1 bit).
Please refer to the
Cyclic Sense Wake-up
discussion for
details of the LPC register setup required for proper Cyclic
Sense or direct wake-up operation.
Table 27. TIM1 Control Bits
CSP2
CSP1
CSP0
Cyclic Sense Timing (ms)
Parameter
0
0
0
5
Cyclic Sense/FWU Timing 1
0
0
1
10
Cyclic Sense/FWU Timing 2
0
1
0
20
Cyclic Sense/FWU Timing 3
0
1
1
40
Cyclic Sense/FWU Timing 4
1
0
0
75
Cyclic Sense/FWU Timing 5
1
0
1
100
Cyclic Sense/FWU Timing 6
1
1
0
200
Cyclic Sense/FWU Timing 7
1
1
1
400
Cyclic Sense/FWU Timing 8
Cyclic Sense Timing, Off Time
Cyclic Sense on Time
t
HS1
Sample
10 μs
HS1 OFF
HS1 ON
Lx Sampling Point
Table 28. LPC Register
LPC
D3
D2
D1
D0
$110B
W
LX2HS1
FWU
HS1AUTO
R
Reset Value
0
0
0
Reset Condition
POR, NR2R
N2R,STB2RSTO2R
POR, NR2R
N2R,STB2RSTO2R
POR, NR2R
N2R,STB2RSTO2R
Table 29. LX2HS1 Control Bits
LX2HS1
Wake-Up Inputs Supplied by HS1
0
No
1
Yes, Lx Inputs Sensed at Sampling Point
Table 30. HS1AUTO Control Bits
HS1AUTO
Auto Timing HS1 in Sleep and Stop Modes
0
OFF
1
ON, HS1 Cyclic, Period Defined in TIM2 Register
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