參數(shù)資料
型號: MCZ33989EG
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip with High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片高高速CAN收發(fā)器
文件頁數(shù): 37/66頁
文件大小: 1181K
代理商: MCZ33989EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Interrupt Register (INT)
This register allows masking or enabling the interrupt
source. A read operation informs about the interrupt source.
When the mask bit is set, INT pin goes low if the
appropriate condition occurs.
If HS1
OT
- V2
LOW
interrupt is only selected (only bit D2 set
in INT register), reading INT register bit D2 leads to two
possibilities:
1. Bit D2 = 1: INT source is HS1OT
2. Bit D2 = 0: INT source is V2LOW
HS1
OT
and V2
LOW
bits status are available in IOR.
Upon a wake-up condition from Stop mode due to over
current detection (I
DD1SW-U1
or I
DD1S-WU2
), an INT pulse is
generated; however, INT register content remains at 0000
(not bit set into the INT register).
The status bit of the INT register content is a copy of the
IOR and CAN registers status content. To clear the INT
register bit the IOR and/or CAN register must be cleared
(read register). Once this operation is done at IOR and CAN
register the INT register is updated.
Errors bits are latched in the CAN register and IOR.
Table 31. INT Register
INT
D3
D2
D1
D0
$111B
W
VSUPLOW
HS1OT-V2LOW
VDDTEMP
CANF
R
VSUPLOW
HS1OT
VDDTEMP
CANF
Reset Value
0
0
0
0
Reset Condition
POR, RST
POR, RST
POR, RST
POR, RST
Table 32. INT Control Bits
Control Bit
Description
CANF
Mask Bit for CAN Failures
V
DDTEMP
Mask Bit for V
DD
Medium Temperature (Pre-Warning)
HS1OT - V2LOW
Mask Bit for HS1 Over Temperature AND V2 Below 4.0 V
V
SUPLOW
Mask Bit for V
SUP
Below 6.1 V
Table 33. INT Status Bits
Status Bit
Description
CANF
CAN Failure
V
DDTEMP
V
DD
Medium Temperature (pre-warning)
HS1OT
HS1 Over Temperature
V
SUPLOW
V
SUP
Below 6.1 V
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