1241
11028E–ATARM–22-Apr-13
SAM9G46
A high data transfer error rate has been observed on the High-Speed USB Host interface when
connected to an external USB Hub. The USB remains functional but the errors may require a
reset of the USB interface to recover.
The Full-Speed USB Host operation is not affected by this problem.
Problem Fix/Workaround
A workaround consists of implementing a timeout on the USB communication using one of the
timers in the device and trigger a reset of the USB Host interface via software and restart the
communication. The impact of the workaround on the data rate is dependent on the error rate
observed in the application but can be such that streaming data at high rates becomes
impractical.
52.2.10
USB High Speed Host Port (UHPHS) and Device Port (UDPHS)
52.2.10.1
UHPHS/UDPHS: USB does not start after power-up
The USB may not start properly at first use after power-up.
If the device boots out of the internal ROM, SAM-BA will not be functional.
Problem Fix/Workaround
1.
Apply a hardware reset (NRST) after power-up.
Or
2.
Activate the PLLUTMI twice, following the procedure below:
– a- Start The UTMI PLL and wait for the PLL lock bit
– b- Disable the UTMI PLL and wait 10 seconds minimum
– c- Restart the UTMIPLL and wait for the PLL Lock bit
Warning: When booting out of the internal ROM, this workaround is not implemented and there-
fore SAMBA will not be functional.
Below is a possible implementation of the workaround:
/* First enable the UTMI PLL */
AT91C_BASE_PMC->CKGR_UCKR |= (AT91C_CKGR_UCKR_PLLCOUNT & (0x3 << 20)) |
AT91C_CKGR_UCKR_UPLLEN;
tmp =0;
while (((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_SR_LOCKU) == 0) && (tmp++ <
DELAY));
/* Disable the PLLUTMI and wait 10s min*/
AT91C_BASE_PMC->CKGR_UCKR &= ~AT91C_CKGR_UCKR_UPLLEN;
tmp=0;
while(tmp++ < DELAY2); // DELAY2 must be defined to fit the 10s min;
/* Re- enable the UTMI PLL and wait for the PLL lock status*/
AT91C_BASE_PMC->CKGR_UCKR |= (AT91C_CKGR_UCKR_PLLCOUNT & (0x3 << 20)) |
AT91C_CKGR_UCKR_UPLLEN;
tmp =0;
while (((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_SR_LOCKU) == 0) && (tmp++ <
DELAY));