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11028E–ATARM–22-Apr-13

When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscil-

lator, the MOSCS bit in PMC_SR (Status Register) is cleared and the counter starts counting

down on the slow clock divided by 8 from the OSCOUNT value. Since the OSCOUNT value is

coded with 8 bits, the maximum startup time is about 62 ms.

When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Set-

ting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor.

Main Oscillator Bypass

The user can input a clock on the device instead of connecting a crystal. In this case, the user

has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin

under these conditions are given in the product electrical characteristics section. The program-

mer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC

Divider and PLLA Block

The PLLA embeds an input divider to increase the accuracy of the resulting clock signals. How-

ever, the user must respect the PLLA minimum input frequency when programming the divider.

The PLLA embeds also an output divisor by 2.

Figure 25-6 shows the block diagram of the divider and PLLA block.

Figure 25-6. Divider and PLLA Block Diagram

Divider and Phase Lock Loop Programming

The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the

output of the corresponding divider and the PLL output is a continuous signal at level 0. On

reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.

The PLLA allows multiplication of the divider’s outputs. The PLLA clock signal has a frequency

that depends on the respective source signal frequency and on the parameters DIVA and

MULA. The factor applied to the source signal frequency is (MULA + 1)/DIVA. When MULA is

written to 0, the PLLA is disabled and its power consumption is saved. Re-enabling the PLLA

can be performed by writing a value higher than 0 in the MUL field.

Whenever the PLLA is re-enabled or one of its parameters is changed, the LOCKA bit in

PMC_SR is automatically cleared. The values written in the PLLACOUNT field in CKGR_PLLAR

are loaded in the PLLA counter. The PLLA counter then decrements at the speed of the Slow

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
MD80C51	制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller
MD80C51BH	制造商:ROCHESTER 制造商全稱:ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space
MD80C51FB	制造商:Rochester Electronics LLC 功能描述:
MD80C86	制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor
MD80C862	制造商:Intel 功能描述:PROCESSOR:MICRO-PROCESSOR

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