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參數(shù)資料
| 型號： | MH28D72KLG-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 9663676416位（134217728 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 4/39頁 |
| 文件大?。?/td> | 337K |
| 代理商： | MH28D72KLG-75 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
4
PIN FUNCTION
CK0,/CK0
Input
Clock: CK0 and /CK0 are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge
of CK0 and negative edge of /CK0. Output (read) data is referenced to
the crossings of CK0 and /CK0 (both directions of crossing).
CKE0, CKE1
Input
Clock Enable: CKE0,1 controls SDRAM internal clock. When CKE0 is low, the
internal clock for the following cycle is ceased. CKE0 is also used to select
auto / self refresh. After self refresh mode is started, CKE0 becomes
asynchronous input. Self refresh is maintained as long as CKE0 is low.
/S0, /S1
Input
Physical Bank Select: When /S0,1 is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12
Input
A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row
Address is specified by A0-12. The Column Address is specified by A0-9,11.
A10 is also used to indicate precharge option. When A10 is high at a read / write
command, an auto precharge is performed. When A10 is high at a precharge
command, all banks are precharged.
BA0,1
Input
DQ 0-64
CB 0-7
Input / Output
DQS0-17
Vdd, VddQ
Power Supply
Power Supply. Vdd and VddQ are connected on the module.
VddQ, VssQ
Power Supply
Bank Address: BA0,1 specifies one of four banks in SDRAM to which a command is applied. BA0,1
must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
SYMBOL
TYPE
DESCRIPTION
Input / Output
Vref
Input
SSTL_2 reference voltage.
Vddspd
Power Supply
Power Supply for SPD
RESET
Input
This signal is asynchronous and is driven low to the register in order to
guarantee the register outputs are low.
SDA
Input / Output
This bidirectional pin is used to transfer data into or out of the SPD EEPROM.
A resistor must be connected from the SDA bus line to VDD to act as a pullup.
SCL
Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor
may be connected from the SCL bus time to VDD to act as a pullup.
SA0-2
These signals are tied at the system planar to either VSS or VDD to configure
the serial SPD EEPROM address range.
Input
VDD identification flag
VDDID
Power Supply. Vss and VssQ are connected on the module.
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