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參數資料
| 型號： | MH28D72KLG-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 9663676416位（134217728 - Word的72位），雙數據速率同步DRAM模塊 |
| 文件頁數： | 13/39頁 |
| 文件大?。?/td> | 337K |
| 代理商： | MH28D72KLG-75 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
13
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM
from damaged or multifunctioning.
1. Apply VDD and VDDQ before or the same time as VTT & Vref
2. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
3. Issue precharge command for all banks of the device
4. Issue EMRS
5. Issue MRS
6. Issue 2 or more Auto Refresh commands
7. Maintain stable condition for 200 cycle
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data until
the next MRS command, which may be issued in idle state.
After tMRD from a MRS command, the DDR DIMM is ready for new
command.
R: Reserved for Future Use
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Burst
Length
BT= 0
R
2
4
8
R
R
R
R
BT= 1
R
2
4
8
R
R
R
R
0
1
Burst
Type
Sequential
Interleaved
A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1 BA0
0
0
DR
0
LTMODE
BT
BL
0
0
0
/S0
/RAS
/CAS
/WE
A11-A0
/CK0
V
CK0
BA0
BA1
CL
Latency
Mode *1
(SDRAM
level)
/CAS Latency
R
R
2
R
R
R
2.5
R
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
DLL
Reset
NO
YES
*1 In the module, 1latency should be added due to registered DIMM.
A12
0
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