參數(shù)資料
型號(hào)： MPC755BVT300LE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 8/56頁(yè)
文件大?。?/td> 0K
描述： MCU HIP4DP 300MHZ 360-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC7xx
處理器類(lèi)型： 32-位 MPC7xx PowerPC
速度： 300MHz
電壓： 2V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 360-BBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 360-FCCBGA（25x25）
包裝： 托盤(pán)
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
16
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 6 provides the input/output timing diagram for the MPC755.
Figure 6. Input/Output Timing Diagram
4.2.3
L2 Clock AC Specifications
The L2CLK frequency is programmed by the L2 configuration register (L2CR[4–6]) core-to-L2 divisor
ratio. See Table 17 for example core and L2 frequencies at various divisors. Table 11 provides the potential
range of L2CLK output AC timing specifications as defined in Figure 7.
The minimum L2CLK frequency of Table 11 is specified by the maximum delay of the internal DLL. The
variable-tap DLL introduces up to a full clock period delay in the L2CLK_OUTA, L2CLK_OUTB, and
L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase-aligned with the next core clock
(divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency
below this minimum, or the L2CLK_OUT signals provided for SRAM clocking will not be phase-aligned
with the MPC755 core clock at the SRAMs.
The maximum L2CLK frequency shown in Table 11 is the core frequency divided by one. Very few L2
SRAM designs will be able to operate in this mode, especially at higher core frequencies. Therefore, most
designs will select a greater core-to-L2 divisor to provide a longer L2CLK period for read and write access
to the L2 SRAMs. The maximum L2CLK frequency for any application of the MPC755 will be a function
of the AC timings of the MPC755, the AC timings for the SRAM, bus loading, and printed-circuit board
trace length. The current AC timing of the MPC755 supports up to 200 MHz with typical, similarly-rated
SRAM parts, provided careful design practices are observed. Clock trace lengths must be matched and all
trace lengths should be as short as possible. Higher frequencies can be achieved by using better performing
SYSCLK
All Inputs
VM
All Outputs
tKHOX
VM
(Except TS, ABB,
ARTRY, DBB)
TS, ABB, DBB
ARTRY
VM
tKHOZ
tKHABPZ
tKHARPZ
tKHARP
tKHOV
tKHOX
tKHOV
tKHOX
tKHOV
tIVKH
tIXKH
tKHOZ
tKHOE
VM = Midpoint Voltage (OVDD/2 or Vin/2)
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參數(shù)描述
MPC755BVT350LE 功能描述:微處理器 - MPU RV2.8,106C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC755CPX350LE 功能描述:微處理器 - MPU 360PBGA,RV2.8,6W RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC755CPX400LE 功能描述:微處理器 - MPU GF RV2.8360PBGA 4A105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC755CPX400LE 制造商:Freescale Semiconductor 功能描述:IC 32BIT MPU 400MHZ BGA-360
MPC755CPX400LER2 功能描述:微處理器 - MPU GF RV2.8360PBGA 4A105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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