參數資料
型號: MPC755CVT400LE
廠商: Freescale Semiconductor
文件頁數: 11/56頁
文件大小: 0K
描述: MCU HIP4DP 400MHZ 360-PBGA
標準包裝: 44
系列: MPC7xx
處理器類型: 32-位 MPC7xx PowerPC
速度: 400MHz
電壓: 2V
安裝類型: 表面貼裝
封裝/外殼: 360-BBGA,FCCBGA
供應商設備封裝: 360-FCCBGA(25x25)
包裝: 托盤
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
19
Electrical and Thermal Characteristics
The L2CLK_OUT timing diagram is shown in Figure 7.
Figure 7. L2CLK_OUT Output Timing Diagram
4.2.4
L2 Bus AC Specifications
Table 12 provides the L2 bus interface AC timing specifications for the MPC755 as defined in Figure 8
and Figure 9 for the loading conditions described in Figure 10.
Table 12. L2 Bus Interface AC Timing Specifications
At recommended operating conditions (see Table 3)
Parameter
Symbol
All Speed Grades
Unit
Notes
Min
Max
L2SYNC_IN rise and fall time
tL2CR, tL2CF
—1.0
ns
1
Setup times: Data and parity
tDVL2CH
1.2
ns
2
Input hold times: Data and parity
tDXL2CH
0—
ns
2
Valid times:
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
tL2CHOV
3.1
3.2
3.3
3.7
ns
3, 4
Output hold times:
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
tL2CHOX
0.5
0.7
0.9
1.1
ns
3
VM = Midpoint Voltage (L2OVDD/2)
L2CLK_OUTA
L2CLK_OUTB
L2 Differential Clock Mode
L2 Single-Ended Clock Mode
L2SYNC_OUT
tL2CLK
tCHCL
L2CLK_OUTA
VM
tL2CR
tL2CF
VM
L2CLK_OUTB
VM
tL2CLK
L2SYNC_OUT
VM
tL2CSKW
tCHCL
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