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參數(shù)資料
| 型號： | MPC755CVT400LE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 31/56頁 |
| 文件大小： | 0K |
| 描述： | MCU HIP4DP 400MHZ 360-PBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | MPC7xx |
| 處理器類型： | 32-位 MPC7xx PowerPC |
| 速度： | 400MHz |
| 電壓： | 2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-BBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 360-FCCBGA（25x25） |
| 包裝： | 托盤 |
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MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
37
System Design Information
The MPC755 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock
frequency of the MPC755. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop
(DLL) circuit and should be routed from the MPC755 to the external RAMs. A separate clock output,
L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin
L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the
clocking of the internal latches in the L2 bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register.
Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the
frequency of the MPC755 core, and the phase adjustment range that the L2 DLL supports. Table 17 shows
various example L2 clock frequencies that can be obtained for a given set of core frequencies. The
minimum L2 frequency target is 80 MHz.
0011
PLL off/bypass
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied
1111
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC755; see Section 4.2.1, “Clock
AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the
bus mode is set for 1:1 mode operation. This mode is intended for factory use and emulator tool use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL off mode, no clocking occurs inside the MPC755 regardless of the SYSCLK input.
Table 17. Sample Core-to-L2 Frequencies
Core Frequency (MHz)
÷1
÷1.5
÷2
÷2.5
÷3
250
166
125
100
83
266
177
133
106
89
275
183
138
110
92
300
200
150
120
100
325
217
163
130
108
333
222
167
133
111
350
233
175
140
117
366
244
183
146
122
Table 16. MPC755 Microprocessor PLL Configuration Example for 400 MHz Parts (continued)
PLL_CFG
[0:3]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus
33 MHz
Bus
50 MHz
Bus
66 MHz
Bus
75 MHz
Bus
80 MHz
Bus
100 MHz
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