參數(shù)資料
型號： MPC8240EC
廠商： Motorola, Inc.
英文描述： Integrated Processor Hardware Specifications
中文描述： 綜合處理器硬件規(guī)格
文件頁數(shù)： 12/52頁
文件大小： 1027K
代理商： MPC8240EC
12
MPC8240 Integrated Processor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Electrical and Thermal Characteristics
clock frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core
frequency; see Section 1.9, “Ordering Information,” for information on ordering parts.
1.4.2.1
AC Operating Frequency Data
Table 6 provides the operating frequency information for the MPC8240.
1.4.2.2
Clock AC Specifications
Table 7 provides the clock AC timing specifications as defined in Section 1.4.2.3, “Input AC Timing
Specifications.”
Table 6. Operating Frequency
At recommended operating conditions (see Table 2) with GV
DD
= 3.3 V ± 5% and LV
DD
= 3.3 V ± 5%
Characteristic
1
200 MHz
250 MHz
2
Unit
Min
Max
Min
Max
Processor frequency (CPU)
100
200
100
250
MHz
Memory bus frequency
33–100
MHz
PCI input frequency
25–66
MHz
Note:
1.
Caution:
The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting
peripheral logic/memory bus frequency and CPU (core) frequency do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.6, “PLL Configurations,”
for valid PLL_CFG[0:4] settings and PCI_SYNC_IN frequencies.
2.) The 250-MHz processor is only available as an R spec part. See Section 1.9.2, “Part Numbers Not Fully Addressed
by This Document,” for more information.
Table 7. Clock AC Timing Specifications
At recommended operating conditions (see Table 2) with LV
DD
= 3.3 V ± 0.3 V
Num
Characteristic and Condition
1
Min
Max
Unit
Notes
1a
Frequency of operation (PCI_SYNC_IN)
25
66
MHz
1b
PCI_SYNC_IN cycle time
40
15
ns
2, 3
PCI_SYNC_IN rise and fall times
—
2.0
ns
2
4
PCI_SYNC_IN duty cycle measured at 1.4 V
40
60
%
5a
PCI_SYNC_IN pulse width high measured at 1.4 V
6
9
ns
3
5b
PCI_SYNC_IN pulse width low measured at 1.4 V
6
9
ns
3
7
PCI_SYNC_IN jitter
—
150
ps
8a
PCI_CLK[0:4] skew (pin-to-pin)
—
500
ps
8b
SDRAM_CLK[0:3] skew (pin-to-pin)
—
350
ps
8
10
Internal PLL relock time
—
100
μs
3, 4, 6
15
DLL lock range with DLL_STANDARD = 1
0
≤
(NT
clk
– t
loop
– t
fix0
)
≤
7
ns
7
F
Freescale Semiconductor, Inc.
n
.
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